intra_pred_pe.tlg

来自「H.264标准解码器全部verilog源码」· TLG 代码 · 共 10 行

Selecting top level module Intra_pred_PE
@N:"E:\Verilog\H.264\Intra_pred_PE.v":1588:7:1588:8|Synthesizing module PE

@N:"E:\Verilog\H.264\Intra_pred_PE.v":18:7:18:19|Synthesizing module Intra_pred_PE

@W:"E:\Verilog\H.264\Intra_pred_PE.v":45:13:45:27|Input port bit <1> of mb_type_general[3:0] is unused

@W:"E:\Verilog\H.264\Intra_pred_PE.v":45:13:45:27|Input port bit <0> of mb_type_general[3:0] is unused