📄 intra_pred_pe.tlg
字号:
Selecting top level module Intra_pred_PE
@N:"E:\Verilog\H.264\Intra_pred_PE.v":1588:7:1588:8|Synthesizing module PE
@N:"E:\Verilog\H.264\Intra_pred_PE.v":18:7:18:19|Synthesizing module Intra_pred_PE
@W:"E:\Verilog\H.264\Intra_pred_PE.v":45:13:45:27|Input port bit <1> of mb_type_general[3:0] is unused
@W:"E:\Verilog\H.264\Intra_pred_PE.v":45:13:45:27|Input port bit <0> of mb_type_general[3:0] is unused
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -