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+access+rwc +notimingcheck +no_tchk_msg +no_specify +librescan +libext+.v+.vp+.mdlp+.vc+.vh+.vm+.sv +define+functional +loadpli1=debpli:deb_PLIPtr +ncnontcglitch +bus_conflict_off //+mixedlang //+de

+access+rwc +notimingcheck +no_tchk_msg +no_specify +librescan +libext+.v+.vp+.mdlp+.vc+.vh+.vm+.sv +define+functional +loadpli1=debpli:deb_PLIPtr +ncnontcglitch +bus_conflict_off //+mixedl

verilog/inc_ifdef.v:1: `line 1 "verilog/inc1.v" 1 verilog/inc_ifdef.v:1: `line 1 "verilog/inc1.v" 0 verilog/inc_ifdef.v:1: `line 1 "verilog/inc2.v" 1 verilog/inc_ifdef.v:1: `line 1 "verilog/inc2.v" 0

#!/usr/bin/perl -w # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package # # Copyright 2000-2009 by Wilson Snyder. This program is free software; # you can redistribute it and/or modify

#!/usr/bin/perl -w # DESCRIPTION: Perl ExtUtils: Type 'make test' to test this package # # Copyright 2000-2009 by Wilson Snyder. This program is free software; # you can redistribute it and/or modify

verilog/v_hier_subprim.v:001: PREPROC '`line 1 "verilog/v_hier_subprim.v" 1 ' verilog/v_hier_subprim.v:008: unreadback ' ' verilog/v_hier_subprim.v:008: KEYWORD 'primitive' verilog/v_hier_subpri

verilog/inc_ifdef.v:1: `line 1 "verilog/inc1.v" 1 verilog/inc_ifdef.v:1: `line 1 "verilog/inc1.v" 0 verilog/inc_ifdef.v:1: `line 1 "verilog/inc2.v" 1 verilog/inc_ifdef.v:1: `line 1 "verilog/inc2.v" 0

verilog/inc_ifdef.v:1: `line 1 "verilog/inc1.v" 1 verilog/inc_ifdef.v:1: `line 1 "verilog/inc1.v" 0 verilog/inc_ifdef.v:1: `line 1 "verilog/inc2.v" 1 verilog/inc_ifdef.v:1: `line 1 "verilog/inc2.v" 0

verilog/v_hier_subprim.v:008: MODULE 'primitive' 'v_hier_prim' undef '0' verilog/v_hier_subprim.v:010: PORT 'q' verilog/v_hier_subprim.v:012: PORT 'a' verilog/v_hier_subprim.v:014: SIGNAL_DECL 'ou

Version 7.2 Build 151 09/26/2007 SJ Full Version 39 2304 OFF OFF OFF OFF ON ON OFF FV_OFF Level2 0 0 VRSM_ON VHSM_ON 0 -- Start Partition -- -- End Partition -- -- Start Library Pat