30_preproc_sub.out

Verilog Parser in Perl

verilog/inc_ifdef.v:1: `line 1 "verilog/inc1.v" 1
verilog/inc_ifdef.v:1: `line 1 "verilog/inc1.v" 0
verilog/inc_ifdef.v:1: `line 1 "verilog/inc2.v" 1
verilog/inc_ifdef.v:1: `line 1 "verilog/inc2.v" 0
verilog/inc_ifdef.v:1: `line 1 "verilog/inc_ifdef.v" 1
COMMENT: // DESCRIPTION: Verilog::Preproc: Example source code
verilog/inc_ifdef.v:1:  /*CMT*/ 
COMMENT: // This file ONLY is placed into the Public Domain, for any use,
verilog/inc_ifdef.v:2:  /*CMT*/ 
COMMENT: // without warranty, 2000-2009 by Wilson Snyder.
verilog/inc_ifdef.v:3:  /*CMT*/ 
verilog/inc_ifdef.v:4: 
verilog/inc_ifdef.v:5:  
verilog/inc_ifdef.v:6:  
verilog/inc_ifdef.v:7:    
verilog/inc_ifdef.v:8: 
verilog/inc_ifdef.v:8: `line 8 "verilog/inc_ifdef.v" 0
verilog/inc_ifdef.v:8: 
verilog/inc_ifdef.v:9: 
verilog/inc_ifdef.v:10:  
verilog/inc_ifdef.v:11:  
verilog/inc_ifdef.v:12:   $display("1A");
verilog/inc_ifdef.v:13:   
verilog/inc_ifdef.v:14:   
verilog/inc_ifdef.v:15:   
verilog/inc_ifdef.v:15: `line 15 "verilog/inc_ifdef.v" 0
verilog/inc_ifdef.v:15: 
verilog/inc_ifdef.v:16:   $display("2A");
verilog/inc_ifdef.v:17:    
verilog/inc_ifdef.v:18:   
verilog/inc_ifdef.v:19:    
verilog/inc_ifdef.v:20:   
verilog/inc_ifdef.v:21:   
verilog/inc_ifdef.v:21: `line 21 "verilog/inc_ifdef.v" 0
verilog/inc_ifdef.v:21: 
verilog/inc_ifdef.v:22:   $display("3AELSE");
verilog/inc_ifdef.v:23:   
verilog/inc_ifdef.v:24:  
verilog/inc_ifdef.v:25:   
verilog/inc_ifdef.v:26:  
verilog/inc_ifdef.v:26: `line 26 "verilog/inc_ifdef.v" 0
verilog/inc_ifdef.v:26: 
verilog/inc_ifdef.v:27:  
verilog/inc_ifdef.v:28:   
verilog/inc_ifdef.v:29:    
verilog/inc_ifdef.v:30:   
verilog/inc_ifdef.v:31:    
verilog/inc_ifdef.v:32:   
verilog/inc_ifdef.v:33:   
verilog/inc_ifdef.v:34:   
verilog/inc_ifdef.v:35:   
verilog/inc_ifdef.v:36:  
verilog/inc_ifdef.v:37:   
verilog/inc_ifdef.v:38: 
verilog/inc_ifdef.v:39:   
verilog/inc_ifdef.v:40: 
verilog/inc_ifdef.v:40: `line 40 "verilog/inc_ifdef.v" 0
verilog/inc_ifdef.v:40: 
verilog/inc_ifdef.v:41: `line 41 "verilog/inc_ifdef.v" 2
verilog/inc_ifdef.v:41: `line 1 "verilog/inc2.v" 0
COMMENT: // DESCRIPTION: Verilog::Preproc: Example source code
verilog/inc2.v:1:  /*CMT*/ 
COMMENT: // This file ONLY is placed into the Public Domain, for any use,
verilog/inc2.v:2:  /*CMT*/ 
COMMENT: // without warranty, 2000-2009 by Wilson Snyder.
verilog/inc2.v:3:  /*CMT*/ 
verilog/inc2.v:4: At file verilog/inc2.v  line 4
verilog/inc3.v:1:  
verilog/inc3.v:1: `line 5 "verilog/inc2.v" 0
verilog/inc3.v:1: `line 1 "verilog/inc3.v" 1
verilog/inc3.v:1: `line 2 "inc3_a_filename_from_line_directive" 0
COMMENT: // DESCRIPTION: Verilog::Preproc: Example source code
inc3_a_filename_from_line_directive:2:  /*CMT*/ 
COMMENT: // This file ONLY is placed into the Public Domain, for any use,
inc3_a_filename_from_line_directive:3:  /*CMT*/ 
COMMENT: // without warranty, 2000-2009 by Wilson Snyder.
inc3_a_filename_from_line_directive:4:  /*CMT*/ 
inc3_a_filename_from_line_directive:5: 
inc3_a_filename_from_line_directive:6:  
inc3_a_filename_from_line_directive:7:   
inc3_a_filename_from_line_directive:8:   
COMMENT: // FOO
inc3_a_filename_from_line_directive:9:    /*CMT*/ 
inc3_a_filename_from_line_directive:10:   At file inc3_a_filename_from_line_directive  line 10
inc3_a_filename_from_line_directive:11: 
inc3_a_filename_from_line_directive:12:    
inc3_a_filename_from_line_directive:13: 
inc3_a_filename_from_line_directive:13: `line 13 "inc3_a_filename_from_line_directive" 0
COMMENT: // guard
inc3_a_filename_from_line_directive:13:   /*CMT*/ 
inc3_a_filename_from_line_directive:14: 
inc3_a_filename_from_line_directive:15:  
inc3_a_filename_from_line_directive:16:   
inc3_a_filename_from_line_directive:17: 
inc3_a_filename_from_line_directive:17: `line 17 "inc3_a_filename_from_line_directive" 0
inc3_a_filename_from_line_directive:17: 
inc3_a_filename_from_line_directive:18: `line 18 "inc3_a_filename_from_line_directive" 2
inc3_a_filename_from_line_directive:18: `line 5 "verilog/inc2.v" 0
verilog/inc2.v:5: 
verilog/inc2.v:6:   
verilog/inc2.v:6: `line 6 "verilog/inc2.v" 2
verilog/inc2.v:6: `line 1 "verilog/inc1.v" 0
COMMENT: // DESCRIPTION: Verilog::Preproc: Example source code
verilog/inc1.v:1:  /*CMT*/ 
COMMENT: // This file ONLY is placed into the Public Domain, for any use,
verilog/inc1.v:2:  /*CMT*/ 
COMMENT: // without warranty, 2000-2009 by Wilson Snyder.
verilog/inc1.v:3:  /*CMT*/ 
verilog/inc1.v:4:    text.
verilog/inc1.v:5: 
COMMENT: /*but not */
COMMENT: /* or this either */
verilog/inc1.v:6:  
COMMENT: // but not
verilog/inc1.v:7:  
COMMENT: /*CMT*/
COMMENT: /*CMT*/
verilog/inc1.v:8: foo   /*CMT*/   bar     /*CMT*/ 
COMMENT: /*CMT*/
verilog/inc1.v:9: foobar2   /*CMT*/ 
verilog/inc1.v:10: 
verilog/inc1.v:11:  
verilog/inc1.v:11: 
verilog/inc1.v:13: 
COMMENT: /*******COMMENT*****/
verilog/inc1.v:14:  /*CMT*/ 
verilog/inc1.v:15: first part  		second part
verilog/inc1.v:16: 
COMMENT: //===========================================================================
verilog/inc1.v:17:  /*CMT*/ 
verilog/inc1.v:18:  
verilog/inc1.v:19: 
verilog/inc1.v:20:  
verilog/inc1.v:21:  
verilog/inc1.v:22: deep deep
verilog/inc1.v:23: 
verilog/inc1.v:24:  
verilog/inc1.v:25:  
verilog/inc1.v:26: "Inside: `nosubst"
verilog/inc1.v:27: "`nosubst"
verilog/inc1.v:28: 
verilog/inc1.v:29:  
verilog/inc1.v:30: x y LLZZ x y
verilog/inc1.v:31: p q LLZZ p q r  s  LLZZ r  s  LLZZ p q LLZZ p q r  s  LLZZ r  s 
verilog/inc1.v:32: 
verilog/inc1.v:33: 
verilog/inc1.v:34: 
verilog/inc1.v:35: firstline	 comma","line LLZZ firstline	 comma","line
verilog/inc1.v:36: 
verilog/inc1.v:37:  
verilog/inc1.v:38: x  y LLZZ "a" y
verilog/inc1.v:39: 
verilog/inc1.v:40:  
verilog/inc1.v:41: (a,b)(a,b)
verilog/inc1.v:42: 
verilog/inc1.v:43:  
verilog/inc1.v:44: $display("left side: \"right side\"")
verilog/inc1.v:45: 
verilog/inc1.v:46:  
verilog/inc1.v:47: bar_suffix  more
verilog/inc1.v:48: 
verilog/inc1.v:49:  
verilog/inc1.v:49: 
verilog/inc1.v:51: $c("Zap(\"",bug1,"\");");;
verilog/inc1.v:52: $c("Zap(\"","bug2","\");");;
verilog/inc1.v:53: 
COMMENT: /* Define inside comment: `DEEPER and `WITHTICK */
verilog/inc1.v:54:  /*CMT*/ 
COMMENT: // More commentary: `zap(bug1); `zap("bug2");
verilog/inc1.v:55:  /*CMT*/ 
verilog/inc1.v:56: 
verilog/inc1.v:57:  
verilog/inc1.v:58:  
verilog/inc1.v:59:    
verilog/inc1.v:60: 
verilog/inc1.v:60: `line 60 "verilog/inc1.v" 0
verilog/inc1.v:60: 
verilog/inc1.v:61: 
COMMENT: //======================================================================
verilog/inc1.v:62:  /*CMT*/ 
COMMENT: // RT bug 34429
verilog/inc1.v:63:  /*CMT*/ 
verilog/inc1.v:64: 
verilog/inc1.v:65:  
verilog/inc1.v:66:  
verilog/inc1.v:67:  
verilog/inc1.v:68:  
COMMENT: // Doesn't expand
verilog/inc1.v:69:  
verilog/inc1.v:70:  
verilog/inc1.v:71:    initial begin
COMMENT: //$display(`msg( \`, \`));  // Illegal
verilog/inc1.v:72:        /*CMT*/ 
verilog/inc1.v:73:       $display("pre thrupre thrumid thrupost post: \"right side\"");
verilog/inc1.v:74:       $display("left side: \"right side\"");
verilog/inc1.v:75:       $display("left side : \"right side \"");
verilog/inc1.v:76:       $display("left_side : \"right_side \"");
verilog/inc1.v:77:       $display("na : \"right_side \"");
verilog/inc1.v:78:       $display("prep ( midp1 left_side midp2 ( outp ) ) : \"right_side \"");
verilog/inc1.v:79:       $display("na: \"nana\"");
COMMENT: // Results vary between simulators
verilog/inc1.v:80:       $display("`ls `rs	 /*CMT*/ : \"`ls `rs	 /*CMT*/ \"");    /*CMT*/ 
COMMENT: // Empty
verilog/inc1.v:81:       $display(": \"\"");   /*CMT*/ 
verilog/inc1.v:82:       $display("left side: \"right side\"");
verilog/inc1.v:83:       $display("left side  : \"right side  \"");
verilog/inc1.v:84: 
verilog/inc1.v:85:  
verilog/inc1.v:85: 
verilog/inc1.v:87:       $display("twoline: \"first   second\"");
verilog/inc1.v:88: 
COMMENT: //$display(`msg(left side, \ right side \ ));  // Not sure \{space} is legal.
verilog/inc1.v:89:        /*CMT*/ 
verilog/inc1.v:90:       $write("*-* All Finished *-*\n");
verilog/inc1.v:91:       $finish;
verilog/inc1.v:92:    end
verilog/inc1.v:93: endmodule
verilog/inc1.v:94: 
verilog/inc1.v:95:  
verilog/inc1.v:95: 
verilog/inc1.v:95: 
verilog/inc1.v:95: 
verilog/inc1.v:99: 
verilog/inc1.v:100: module add1 ( input wire d1, output wire o1);
COMMENT: // expansion is OK
verilog/inc1.v:101:  wire  tmp_d1 = d1;  wire  tmp_o1 = tmp_d1 + 1;  assign o1 = tmp_o1 ;    /*CMT*/ 
verilog/inc1.v:102: endmodule
verilog/inc1.v:103: module add2 ( input wire d2, output wire o2);
COMMENT: // expansion is bad
verilog/inc1.v:104:  wire  tmp_d2  = d2 ;  wire  tmp_o2  = tmp_d2  + 1;  assign o2  = tmp_o2  ;   /*CMT*/ 
verilog/inc1.v:105: endmodule
verilog/inc1.v:106: 
COMMENT: //======================================================================
verilog/inc1.v:107:  /*CMT*/ 
COMMENT: // Quotes are legal in protected blocks.  Grr.
verilog/inc1.v:108:  /*CMT*/ 
verilog/inc1.v:109: module prot();
verilog/inc1.v:110: `protected
verilog/inc1.v:110:     I!#r#e6<_Q{{E2+]I3<[3s)1@D|'E''i!O?]jD>Jo_![Cl)
verilog/inc1.v:110:     #nj1]p,3^1~,="E@QZB\T)eU\pC#C|7=\$J$##A[@-@{Qk]
verilog/inc1.v:113: `endprotected
verilog/inc1.v:114: endmodule
COMMENT: //"
verilog/inc1.v:115:  /*CMT*/ 
verilog/inc1.v:116: 
COMMENT: //======================================================================
verilog/inc1.v:117:  /*CMT*/ 
COMMENT: // macro call with define that has comma
verilog/inc1.v:118:  /*CMT*/ 
verilog/inc1.v:119:  
verilog/inc1.v:120:  
verilog/inc1.v:121:  
verilog/inc1.v:122:  
verilog/inc1.v:123:  
verilog/inc1.v:124:  
verilog/inc1.v:125:  
verilog/inc1.v:126: 
verilog/inc1.v:127: begin addr <= (({regs[6], regs[7]} + 1)); rd <= 1; end and begin addr <= (({regs[6], regs[7]})); wdata <= (rdata); wr <= 1; end
verilog/inc1.v:128: begin addr <= ({regs[6], regs[7]} + 1); rd <= 1; end
verilog/inc1.v:129: begin addr <= ({regs[6], regs[7]}); wdata <= (rdata); wr <= 1; end  more
verilog/inc1.v:130: 
COMMENT: //======================================================================
verilog/inc1.v:131:  /*CMT*/ 
COMMENT: // include of parameterized file
verilog/inc1.v:132:  /*CMT*/ 
verilog/inc1.v:133:  
verilog/inc4.v:1:  
verilog/inc4.v:1: `line 134 "verilog/inc1.v" 0
verilog/inc4.v:1: `line 1 "verilog/inc4.v" 1
COMMENT: // DESCRIPTION: Verilog::Preproc: Example source code
verilog/inc4.v:1:  /*CMT*/ 
COMMENT: // This file ONLY is placed into the Public Domain, for any use,
verilog/inc4.v:2:  /*CMT*/ 
COMMENT: // without warranty, 2000-2009 by Wilson Snyder.
verilog/inc4.v:3:  /*CMT*/ 
verilog/inc4.v:4: 
verilog/inc4.v:5:  
verilog/inc4.v:6: `line 6 "verilog/inc4.v" 2
verilog/inc4.v:6: `line 134 "verilog/inc1.v" 0
verilog/inc1.v:134: 
verilog/inc1.v:135:  
verilog/inc1.v:136:   
verilog/inc1.v:137: 
verilog/inc1.v:137: `line 137 "verilog/inc1.v" 0
verilog/inc1.v:137: 
verilog/inc1.v:138:  
verilog/inc1.v:139: 
verilog/inc1.v:140:  
verilog/inc1.v:141:   
verilog/inc1.v:142: 
verilog/inc1.v:142: `line 142 "verilog/inc1.v" 0
verilog/inc1.v:142: 
verilog/inc1.v:143: 
COMMENT: //======================================================================
verilog/inc1.v:144:  /*CMT*/ 
COMMENT: // macro call with , in {}
verilog/inc1.v:145:  /*CMT*/ 
verilog/inc1.v:146: 
verilog/inc1.v:147:  
verilog/inc1.v:148: $blah("ab,cd","e,f");
verilog/inc1.v:149: $blah(this.log,vec);
verilog/inc1.v:150: $blah(this.log,vec[1,2,3]);
verilog/inc1.v:151: $blah(this.log,{blah.name(), " is not foo"});
verilog/inc1.v:152: 
COMMENT: //======================================================================
verilog/inc1.v:153:  /*CMT*/ 
COMMENT: // pragma/default net type
verilog/inc1.v:154:  /*CMT*/ 
verilog/inc1.v:155: 
verilog/inc1.v:156: `pragma foo = 1
verilog/inc1.v:157: `default_nettype none
verilog/inc1.v:158: `default_nettype uwire
verilog/inc1.v:159: `line 159 "verilog/inc1.v" 2