files_tg2011.lst

spi slave 8bit address 1bit r/w 7bit number data

+access+rwc
+notimingcheck
+no_tchk_msg
+no_specify
+librescan
+libext+.v+.vp+.mdlp+.vc+.vh+.vm+.sv
+define+functional
+loadpli1=debpli:deb_PLIPtr
+ncnontcglitch
+bus_conflict_off 
//+mixedlang 
//+define+FULLCHIP 


//----------------------------------------------------------------------------
// User
//----------------------------------------------------------------------------
        +incdir+.+../rtl
        +incdir+.+../mem
	+incdir+../model/i2cm
	+incdir+../model/i2cm_if_model
	+incdir+../model/tg2011
	+incdir+../model/csu

        +incdir+/home_wing/tools/synopsys/2003.12-SP1/SYN/packages/gtech/src_ver
        +incdir+/home_wing/tools/synopsys/2003.12-SP1/SYN/dw/dw01/src_ver
        +incdir+/home_wing/tools/synopsys/2003.12-SP1/SYN/dw/dw02/src_ver
        +incdir+/home_wing/tools/synopsys/2003.12-SP1/SYN/dw/dw06/src_ver
/*
	+incdir+../../../../library/xilinx_8.1/verilog
	+incdir+../../../../library/xilinx_8.1/verilog/XilinxCoreLib
	+incdir+../../../../library/xilinx_8.1/verilog/simprims
	+incdir+../../../../library/xilinx_8.1/verilog/unisims
*/
// Models
        -y ../model/i2cm
        -y ../model/i2cm_if_model
        -y ../model/tg2011
        -v ../model/csu/csu.v
        -v ../model/csu/csu_logic.vp
        -v ../model/csu/csu_1ch.v
        -v ../model/csu/csu_logic_1ch.vp
        -v ../model/csu/csu_analog_model.vp
        -v ../model/csu/RCOSC.vm
        -v ../model/csu/SOSC.vm
        -v ../model/csu/LDO18A_DAC.v
        -v ../model/csu/LDO18A_100M_R2.v

// Source
        -y ../rtl
        -y ../mem

// Test Bench File
        ./tb_tg2011.v
        ./stm_i2c.v
        //./stm_ts.v


//----------------------------------------------------------------------------
// Root
//----------------------------------------------------------------------------
/*
        +incdir+.+/applec/project/seda-mpeg4/rtl/ae32kc
        +incdir+/applec/project/seda-mpeg4/rtl/mpeg4
        +incdir+/applec/project/seda-mpeg4/rtl/top
        +incdir+/applec/project/seda-mpeg4/model/top
        +incdir+/applec/project/seda-mpeg4/tdrv

        +incdir+/lilyb/tools/synV200406SP2/dw/dw01/src_ver
        +incdir+/lilyb/tools/synV200406SP2/dw/dw02/src_ver
        +incdir+/lilyb/tools/synV200406SP2/dw/dw06/src_ver

// Models
        -y /applec/project/seda-mpeg4/model/top
        -y /applec/project/seda-mpeg4/tdrv

// Source
        -y /applec/project/seda-mpeg4/rtl/ae32kc
        -y /applec/project/seda-mpeg4/rtl/mpeg4
        -y /applec/project/seda-mpeg4/rtl/top
	-v /applec/project/seda-mpeg4/rtl/mpeg4/mpeg4_core.vp

// Test Bench File
        /applec/project/seda-mpeg4/func_sim/tb_sedampeg4.v
*/

//----------------------------------------------------------------------------
// Library
//----------------------------------------------------------------------------
// Synopsys Design Ware
	-y /home_wing/tools/synopsys/2003.12-SP1/SYN/packages/gtech/src_ver 
	-y /home_wing/tools/synopsys/2003.12-SP1/SYN/dw/dw01/src_ver 
	-y /home_wing/tools/synopsys/2003.12-SP1/SYN/dw/dw02/src_ver 
	-y /home_wing/tools/synopsys/2003.12-SP1/SYN/dw/dw06/src_ver 

// Xilinx Library for FPGA
	-v ../../../../library/xilinx_8.1/verilog/glbl.v
	-y ../../../../library/xilinx_8.1/verilog/XilinxCoreLib
	-y ../../../../library/xilinx_8.1/verilog/simprims
	-y ../../../../library/xilinx_8.1/verilog/unisims

// Chartered 0.18um Library
	-v ../../../../TG901/LIB/IC/sc-x/verilog/csm18ic.v
	-v ../../../../TG901/LIB/IC/IO/io-il/verilog/iogp_il_csm18ic_verilog.v

// SMIC 0.18um Library
//	-v /proj/techlib/smic/018um/release/2005q4v1/vlog/smic18.v 
//	-v /proj/techlib/smic/018um/release/2005q4v1/vlog/SP018W_V1p7.v 
//	-v /proj/techlib/smic/018um/release/2005q4v1/S018PLLGS_500_EDK_V_1_4_4/vlog/S018PLLGS_500.v 
//	-v /proj/techlib/smic/018um/release/2005q4v1/smic18_ICG/v1.1/vlog/smic18_GC.v 
//	-y /proj/techlib/smic/018um/release/2005q4v1/mem/vlog