30_preproc_nows.out

Verilog Parser in Perl

verilog/inc_ifdef.v:1: `line 1 "verilog/inc1.v" 1
verilog/inc_ifdef.v:1: `line 1 "verilog/inc1.v" 0
verilog/inc_ifdef.v:1: `line 1 "verilog/inc2.v" 1
verilog/inc_ifdef.v:1: `line 1 "verilog/inc2.v" 0
verilog/inc_ifdef.v:1: `line 1 "verilog/inc_ifdef.v" 1
verilog/inc_ifdef.v:8: `line 8 "verilog/inc_ifdef.v" 0
verilog/inc_ifdef.v:12:  $display("1A");
verilog/inc_ifdef.v:15: `line 15 "verilog/inc_ifdef.v" 0
verilog/inc_ifdef.v:16:  $display("2A");
verilog/inc_ifdef.v:21: `line 21 "verilog/inc_ifdef.v" 0
verilog/inc_ifdef.v:22:  $display("3AELSE");
verilog/inc_ifdef.v:26: `line 26 "verilog/inc_ifdef.v" 0
verilog/inc_ifdef.v:40: `line 40 "verilog/inc_ifdef.v" 0
verilog/inc_ifdef.v:41: `line 41 "verilog/inc_ifdef.v" 2
verilog/inc_ifdef.v:41: `line 1 "verilog/inc2.v" 0
verilog/inc2.v:4: At file verilog/inc2.v line 4
verilog/inc3.v:1: `line 5 "verilog/inc2.v" 0
verilog/inc3.v:1: `line 1 "verilog/inc3.v" 1
verilog/inc3.v:1: `line 2 "inc3_a_filename_from_line_directive" 0
inc3_a_filename_from_line_directive:10:  At file inc3_a_filename_from_line_directive line 10
inc3_a_filename_from_line_directive:13: `line 13 "inc3_a_filename_from_line_directive" 0
inc3_a_filename_from_line_directive:17: `line 17 "inc3_a_filename_from_line_directive" 0
inc3_a_filename_from_line_directive:18: `line 18 "inc3_a_filename_from_line_directive" 2
inc3_a_filename_from_line_directive:18: `line 5 "verilog/inc2.v" 0
verilog/inc2.v:6: `line 6 "verilog/inc2.v" 2
verilog/inc2.v:6: `line 1 "verilog/inc1.v" 0
verilog/inc1.v:4:  text.
verilog/inc1.v:8: foo bar
verilog/inc1.v:9: foobar2
verilog/inc1.v:15: first part second part
verilog/inc1.v:22: deep deep
verilog/inc1.v:26: "Inside: `nosubst"
verilog/inc1.v:27: "`nosubst"
verilog/inc1.v:30: x y LLZZ x y
verilog/inc1.v:31: p q LLZZ p q r s LLZZ r s LLZZ p q LLZZ p q r s LLZZ r s 
verilog/inc1.v:35: firstline comma","line LLZZ firstline comma","line
verilog/inc1.v:38: x y LLZZ "a" y
verilog/inc1.v:41: (a,b)(a,b)
verilog/inc1.v:44: $display("left side: \"right side\"")
verilog/inc1.v:47: bar_suffix more
verilog/inc1.v:51: $c("Zap(\"",bug1,"\");");;
verilog/inc1.v:52: $c("Zap(\"","bug2","\");");;
verilog/inc1.v:60: `line 60 "verilog/inc1.v" 0
verilog/inc1.v:71:  initial begin
verilog/inc1.v:73:  $display("pre thrupre thrumid thrupost post: \"right side\"");
verilog/inc1.v:74:  $display("left side: \"right side\"");
verilog/inc1.v:75:  $display("left side : \"right side \"");
verilog/inc1.v:76:  $display("left_side : \"right_side \"");
verilog/inc1.v:77:  $display("na : \"right_side \"");
verilog/inc1.v:78:  $display("prep ( midp1 left_side midp2 ( outp ) ) : \"right_side \"");
verilog/inc1.v:79:  $display("na: \"nana\"");
verilog/inc1.v:80:  $display("`ls `rs : \"`ls `rs \""); 
verilog/inc1.v:81:  $display(": \"\""); 
verilog/inc1.v:82:  $display("left side: \"right side\"");
verilog/inc1.v:83:  $display("left side  : \"right side  \"");
verilog/inc1.v:87:  $display("twoline: \"first   second\"");
verilog/inc1.v:90:  $write("*-* All Finished *-*\n");
verilog/inc1.v:91:  $finish;
verilog/inc1.v:92:  end
verilog/inc1.v:93: endmodule
verilog/inc1.v:100: module add1 ( input wire d1, output wire o1);
verilog/inc1.v:101:  wire tmp_d1 = d1; wire tmp_o1 = tmp_d1 + 1; assign o1 = tmp_o1 ; 
verilog/inc1.v:102: endmodule
verilog/inc1.v:103: module add2 ( input wire d2, output wire o2);
verilog/inc1.v:104:  wire tmp_d2 = d2 ; wire tmp_o2 = tmp_d2 + 1; assign o2 = tmp_o2 ; 
verilog/inc1.v:105: endmodule
verilog/inc1.v:109: module prot();
verilog/inc1.v:110: `protected
verilog/inc1.v:110:     I!#r#e6<_Q{{E2+]I3<[3s)1@D|'E''i!O?]jD>Jo_![Cl)
verilog/inc1.v:110:     #nj1]p,3^1~,="E@QZB\T)eU\pC#C|7=\$J$##A[@-@{Qk]
verilog/inc1.v:113: `endprotected
verilog/inc1.v:114: endmodule
verilog/inc1.v:127: begin addr <= (({regs[6], regs[7]} + 1)); rd <= 1; end and begin addr <= (({regs[6], regs[7]})); wdata <= (rdata); wr <= 1; end
verilog/inc1.v:128: begin addr <= ({regs[6], regs[7]} + 1); rd <= 1; end
verilog/inc1.v:129: begin addr <= ({regs[6], regs[7]}); wdata <= (rdata); wr <= 1; end more
verilog/inc4.v:1: `line 134 "verilog/inc1.v" 0
verilog/inc4.v:1: `line 1 "verilog/inc4.v" 1
verilog/inc4.v:6: `line 6 "verilog/inc4.v" 2
verilog/inc4.v:6: `line 134 "verilog/inc1.v" 0
verilog/inc1.v:137: `line 137 "verilog/inc1.v" 0
verilog/inc1.v:142: `line 142 "verilog/inc1.v" 0
verilog/inc1.v:148: $blah("ab,cd","e,f");
verilog/inc1.v:149: $blah(this.log,vec);
verilog/inc1.v:150: $blah(this.log,vec[1,2,3]);
verilog/inc1.v:151: $blah(this.log,{blah.name(), " is not foo"});
verilog/inc1.v:156: `pragma foo = 1
verilog/inc1.v:157: `default_nettype none
verilog/inc1.v:158: `default_nettype uwire
verilog/inc1.v:159: `line 159 "verilog/inc1.v" 2