代码搜索结果
找到约 10,000 项符合
Verilog 的代码
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity textram is
port(
addr : in vl_logic_vector(12 downto 0);
clk : in vl_logic;
din
full_adder.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity glbl is
generic(
ROC_WIDTH : integer := 100000;
TOC_WIDTH : integer := 0
);
end glbl;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity save is
port(
clka : in vl_logic;
dina : in vl_logic_vector(0 downto 0);
addra : i
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity vga is
port(
clk : in vl_logic;
rst : in vl_logic;
sw2 : in vl_logic;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity sendsave is
port(
clk : in vl_logic;
rst : in vl_logic;
ssra : out vl_logic;
_primary.vhd
library verilog;
use verilog.vl_types.all;
entity savecon is
port(
clk : in vl_logic;
rst : in vl_logic;
date : in vl_logic;
case3s.v
//*********************************************************
// IEEE STD 1364-1995 Verilog file: case3s.v
// Author-EMAIL: Uwe.Meyer-Baese@ieee.org
//************************************************
case3s.v
//*********************************************************
// IEEE STD 1364-1995 Verilog file: case3s.v
// Author-EMAIL: Uwe.Meyer-Baese@ieee.org
//************************************************
lfsr.v
//*********************************************************
// IEEE STD 1364-1995 Verilog file: lfsr.v
// Author-EMAIL: Uwe.Meyer-Baese@ieee.org
//**************************************************