_primary.vhd

来自「利用VERILOG编写的基于XILINX的SPARTAN板的VGA接口显示程序」· VHDL 代码 · 共 17 行

library verilog;
use verilog.vl_types.all;
entity vga is
    port(
        clk             : in     vl_logic;
        rst             : in     vl_logic;
        sw2             : in     vl_logic;
        sw3             : in     vl_logic;
        hs              : out    vl_logic;
        vs              : out    vl_logic;
        red             : out    vl_logic_vector(2 downto 0);
        green           : out    vl_logic_vector(2 downto 0);
        blue            : out    vl_logic_vector(1 downto 0);
        addrb           : out    vl_logic_vector(14 downto 0)
    );
end vga;