_primary.vhd

来自「利用VERILOG编写的基于XILINX的SPARTAN板的VGA接口显示程序」· VHDL 代码 · 共 18 行

library verilog;
use verilog.vl_types.all;
entity savecon is
    port(
        clk             : in     vl_logic;
        rst             : in     vl_logic;
        date            : in     vl_logic;
        sw3             : in     vl_logic;
        counths         : in     vl_logic_vector(9 downto 0);
        countvs         : in     vl_logic_vector(9 downto 0);
        red             : out    vl_logic_vector(2 downto 0);
        green           : out    vl_logic_vector(2 downto 0);
        blue            : out    vl_logic_vector(1 downto 0);
        addre2          : out    vl_logic_vector(14 downto 0);
        web             : out    vl_logic
    );
end savecon;