_primary.vhd

来自「利用VERILOG编写的基于XILINX的SPARTAN板的VGA接口显示程序」· VHDL 代码 · 共 14 行

library verilog;
use verilog.vl_types.all;
entity sendsave is
    port(
        clk             : in     vl_logic;
        rst             : in     vl_logic;
        ssra            : out    vl_logic;
        sw2             : in     vl_logic;
        addr            : out    vl_logic_vector(14 downto 0);
        din             : out    vl_logic;
        wea             : out    vl_logic
    );
end sendsave;