_primary.vhd

来自「利用VERILOG编写的基于XILINX的SPARTAN板的VGA接口显示程序」· VHDL 代码 · 共 18 行

library verilog;
use verilog.vl_types.all;
entity save is
    port(
        clka            : in     vl_logic;
        dina            : in     vl_logic_vector(0 downto 0);
        addra           : in     vl_logic_vector(14 downto 0);
        wea             : in     vl_logic_vector(0 downto 0);
        ssra            : in     vl_logic;
        douta           : out    vl_logic_vector(0 downto 0);
        clkb            : in     vl_logic;
        dinb            : in     vl_logic_vector(0 downto 0);
        addrb           : in     vl_logic_vector(14 downto 0);
        web             : in     vl_logic_vector(0 downto 0);
        doutb           : out    vl_logic_vector(0 downto 0)
    );
end save;