代码搜索：Verilog
找到约 10,000 项符合「Verilog」的源代码
代码结果 10,000
www.eeworm.com/read/224217/14601616
qsf taix_fee.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
www.eeworm.com/read/221711/14726578
qmsg div.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info:
www.eeworm.com/read/221708/14727696
qmsg traffic.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info:
www.eeworm.com/read/219734/14866802
sap mult_tst.sap
n work Mult_tst_v verilog;
av .syn_compile_point 1;
av .compile_point_name Mult_tst_v;
www.eeworm.com/read/219733/14866898
sap people4.sap
n work people4 verilog;
av .syn_compile_point 1;
av .compile_point_name people4;
www.eeworm.com/read/215972/15031609
npl gold_code_ver_217.npl
JDF G
// Created by Project Navigator ver 1.0
PROJECT Untitled
DESIGN gold_code_ver_217
DEVFAM virtex
DEVFAMTIME 1016217515
DEVICE xcv300
DEVICETIME 1016217515
DEVPKG bg432
DEVPKGTIME 1016217
www.eeworm.com/read/214883/15085103
_prj iq_pn_gen._prj
insert `timescale 1ns/1ns
include
include iq_pn_gen.v
include D:/Xilinx/verilog/src/iSE/unisim_comp.v
www.eeworm.com/read/214813/15087259
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity machinect1 is
port(
ena : out vl_logic;
fetch : in vl_logic;
rst : in vl_logi
www.eeworm.com/read/207756/15262677
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity mult is
generic(
w2 : integer := 17;
w1 : integer := 9;
w : integer := 8
);
www.eeworm.com/read/207756/15262683
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity add is
generic(
w2 : integer := 17
);
port(
dataa : in vl_logic_vector;
datab