gold_code_ver_217.npl

gold_code_ver_217 源程序

JDF G
// Created by Project Navigator ver 1.0
PROJECT Untitled
DESIGN gold_code_ver_217
DEVFAM virtex
DEVFAMTIME 1016217515
DEVICE xcv300
DEVICETIME 1016217515
DEVPKG bg432
DEVPKGTIME 1016217515
DEVSPEED -6
DEVSPEEDTIME 1016217515
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Modelsim
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL Verilog
GENERATEDSIMULATIONMODELTIME 0
DOCUMENT readme
STIMULUS testbench.tf
SOURCE infer.v
SOURCE sub_a.v
SOURCE sub_b.v
[Normal]
p_ModelSimSimRunTime_tb=xstvlg, virtex, Test Fixture.t_MSimulatePostTranslateVerilogModel, 1054564257, 5000ns
[STRATEGY-LIST]
Normal=True