_primary.vhd

来自「在ise下设计的蝶形变换程序」· VHDL 代码 · 共 15 行

library verilog;
use verilog.vl_types.all;
entity mult is
    generic(
        w2              : integer := 17;
        w1              : integer := 9;
        w               : integer := 8
    );
    port(
        dataa           : in     vl_logic_vector;
        datab           : in     vl_logic_vector;
        result          : out    vl_logic_vector
    );
end mult;