_primary.vhd

来自「精简CPU设计」· VHDL 代码 · 共 10 行

library verilog;
use verilog.vl_types.all;
entity machinect1 is
    port(
        ena             : out    vl_logic;
        fetch           : in     vl_logic;
        rst             : in     vl_logic
    );
end machinect1;