代码搜索：Verilog
找到约 10,000 项符合「Verilog」的源代码
代码结果 10,000
www.eeworm.com/read/172338/9713048
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity can_testbench is
generic(
tp : integer := 1;
brp : integer := 4
);
end can_testbench;
www.eeworm.com/read/415978/11046302
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity sdr_sdram_tb is
port(
);
end sdr_sdram_tb;
www.eeworm.com/read/415978/11046354
prj sdr_sdram.prj
#-- Synplicity, Inc.
#-- Version 6.0
#-- Project file d:\projects\altera\lpcores\sdr\release\v1_2\synthesis\synplicity\sdr_sdram.prj
#-- Written on Thu Jul 06 17:54:29 2000
#add_file options
www.eeworm.com/read/268989/11112289
txt 元件例化与层次设计.txt
Verilog HDL: Creating a Hierarchical Design
This example describes how to create a hierarchical design using Verilog HDL.
The file top_ver.v is the top level, which calls the two lower level file
www.eeworm.com/read/412328/11204404
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity latch_rp is
// This module cannot be connected to from
// VHDL because it has unnamed ports.
end latch_rp;
www.eeworm.com/read/265648/11258738
_prj buzz2._prj
insert `timescale 1ns/1ns
include
include buzz2.v
include d:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v
www.eeworm.com/read/265648/11258743
_prj buzz1._prj
insert `timescale 1ns/1ns
include
include buzz1.v
include d:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v
www.eeworm.com/read/265644/11259151
_prj pwm._prj
insert `timescale 1ns/1ns
include
include pwm1.v
include d:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v
www.eeworm.com/read/265644/11259181
npl pwm1.npl
JDF E
// Created by ISE ver 1.0
PROJECT pwm1
DESIGN pwm1 Normal
DEVKIT XC95108 PC84
DEVFAM xc9500
FLOW XST Verilog
MODULE pwm1.v
MODSTYLE pwm Normal
[STRATEGY-LIST]
Normal=True, 1037612277
www.eeworm.com/read/265643/11259204
_prj clock._prj
insert `timescale 1ns/1ns
include
include clock.v
include d:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v