sdr_sdram.prj

来自「Altera 官方提供的SDRAM控制器,verilog的」· PRJ 代码 · 共 45 行

#-- Synplicity, Inc.
#-- Version 6.0
#-- Project file d:\projects\altera\lpcores\sdr\release\v1_2\synthesis\synplicity\sdr_sdram.prj
#-- Written on Thu Jul 06 17:54:29 2000


#add_file options
add_file -verilog "d:/projects/altera/lpcores/sdr/release/v1_2/source/control_interface.v"
add_file -verilog "d:/projects/altera/lpcores/sdr/release/v1_2/source/sdr_data_path.v"
add_file -verilog "d:/projects/altera/lpcores/sdr/release/v1_2/source/command.v"
add_file -verilog "d:/projects/altera/lpcores/sdr/release/v1_2/source/pll1.v"
add_file -verilog "d:/projects/altera/lpcores/sdr/release/v1_2/source/sdr_sdram.v"


#implementation: "ver1"
impl -name ver1

#device options
set_option -technology APEX20K
set_option -part EP20K400E
set_option -package FC672
set_option -speed_grade -1X

#compilation/mapping options
set_option -default_enum_encoding default
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 1

#map options
set_option -frequency 133.000
set_option -domap 1
set_option -disable_io_insertion 0
set_option -cliquing 1
set_option -pipe 0

#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "ver1/sdr_sdram.vqm"