代码搜索：Verilog
找到约 10,000 项符合「Verilog」的源代码
代码结果 10,000
www.eeworm.com/read/214382/15103996
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ddr_sdram_tb is
port(
);
end ddr_sdram_tb;
www.eeworm.com/read/213395/15135652
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity clkgen is
generic(
idle : integer := 0;
q1 : integer := 1;
q2 : integer := 2;
www.eeworm.com/read/213395/15135683
ant default.ant
// E:\FPGA\CLKGEN
// Verilog Annotation Test Bench created by
// HDL Bencher 6.1i
// Thu Apr 05 11:33:31 2007
`timescale 1ns/1ns
module wave;
UUT (
);
integer TX_FILE;
integer TX
www.eeworm.com/read/207756/15262667
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity jiajia is
port(
A : in vl_logic_vector(7 downto 0);
B : in vl_logic_vector(7 downto 0);
www.eeworm.com/read/207756/15262695
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity test is
generic(
PERIOD : integer := 200;
DUTY_CYCLE : real := 0.500000;
OFFSET : integer := 0
www.eeworm.com/read/207756/15262698
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity yuan is
port(
yu : out vl_logic
);
end yuan;
www.eeworm.com/read/206514/15294014
prj iq_pn_gen.prj
`timescale 1ns/1ns
`include "iq_pn_gen.v"
`include "D:/Xilinx/verilog/src/iSE/unisim_comp.v"
www.eeworm.com/read/173096/5380346
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity csa8_4 is
port(
a1 : in vl_logic_vector(3 downto 0);
a2 : in vl_logic_vector(3 downto 0);
www.eeworm.com/read/173096/5380362
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity comp is
port(
a1 : in vl_logic_vector(3 downto 0);
a2 : in vl_logic_vector(3 downto 0);
www.eeworm.com/read/168634/5441120
compileformti
#!/bin/csh -f
if (-e work) then
\rm -rf work
endif
vlib work
vlog \
-v ../verilog/src/mem.v \
../verilog/RTL/TopModule.v \
../verilog/RTL/ALUB.v \
../verilog/RTL/CCU.v \
../verilog/FSM/master.v