default.ant

verilog 编写的pic16c5x时钟模块

// E:\FPGA\CLKGEN
// Verilog Annotation Test Bench created by
// HDL Bencher 6.1i
// Thu Apr 05 11:33:31 2007

`timescale 1ns/1ns

module wave;

	 UUT (
	);

	integer TX_FILE;
	integer TX_ERROR;

always begin // Annotate outputs process