clkgen.ldo

来自「verilog 编写的pic16c5x时钟模块」· LDO 代码 · 共 13 行

# Auto generated by Project Navigator for Modelsim
vlib work

vlog  clkgen.v
vlog  "C:/Xilinx/verilog/src/glbl.v"
## You need to generate your own stimuli
vsim -t 1ps +maxdelays -L xilinxcorelib_ver -L unisims_ver  clkgen glbl

view wave
add wave *
view structure
view signals