_primary.vhd

来自「在ise下设计的蝶形变换程序」· VHDL 代码 · 共 10 行

library verilog;
use verilog.vl_types.all;
entity test is
    generic(
        PERIOD          : integer := 200;
        DUTY_CYCLE      : real    := 0.500000;
        OFFSET          : integer := 0
    );
end test;