_primary.vhd

精通VerilogHDL：IC设计核心技术实例详解

library verilog;
use verilog.vl_types.all;
entity csa8_4 is
    port(
        a1              : in     vl_logic_vector(3 downto 0);
        a2              : in     vl_logic_vector(3 downto 0);
        a3              : in     vl_logic_vector(3 downto 0);
        a4              : in     vl_logic_vector(3 downto 0);
        a5              : in     vl_logic_vector(3 downto 0);
        a6              : in     vl_logic_vector(3 downto 0);
        a7              : in     vl_logic_vector(3 downto 0);
        a8              : in     vl_logic_vector(3 downto 0);
        sum             : out    vl_logic_vector(7 downto 0)
    );
end csa8_4;