代码搜索：Verilog
找到约 10,000 项符合「Verilog」的源代码
代码结果 10,000
www.eeworm.com/read/221711/14726499
qmsg cmp.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info:
www.eeworm.com/read/221711/14727115
qmsg encode.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info:
www.eeworm.com/read/219734/14866744
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity Mult is
port(
a : in vl_logic_vector(7 downto 0);
b : in vl_logic_vector(7 downto 0);
www.eeworm.com/read/219734/14866832
log syntax.log
$ Start of Compile
#Tue Nov 07 08:49:38 2006
Synplicity Verilog Compiler, version 3.6t, Build 139R, built Jun 15 2006
Copyright (C) 1994-2006, Synplicity Inc. All Rights Reserved
@E|Can't ope
www.eeworm.com/read/219731/14867388
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity time24 is
port(
cin : in vl_logic_vector(0 downto 0);
clr : in vl_logic_vector(0 downto 0);
www.eeworm.com/read/217283/14970662
prj clockdiv_tbw_par.prj
verilog work "netgen/par/ClockDiv_timesim.v"
vhdl work "ClockDiv_tbw.vhw"
verilog work "C:/Xilinx/verilog/src/glbl.v"
www.eeworm.com/read/214883/15085085
prj iq_pn_gen.prj
`timescale 1ns/1ns
`include "iq_pn_gen.v"
`include "D:/Xilinx/verilog/src/iSE/unisim_comp.v"
www.eeworm.com/read/214813/15087243
_info
m255
13
cModel Technology
dE:\feng\verilog\simic
vaccum
I@oXABY1>6n`Y`7`UHcLAP3
VmPUj`9SMUSV@3j:DGGFIa3
dE:\feng\verilog\riscmcu
w1163157778
FE:/feng/verilog/riscmcu/accum.v
L0 1
VmPUj`9SMUSV@3j:DGGFI
www.eeworm.com/read/214503/15098145
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity adder4_adder4t_v_tf is
end adder4_adder4t_v_tf;
www.eeworm.com/read/214502/15098337
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity song_songt_v_tf is
end song_songt_v_tf;