syntax.log

这是我自己写的两个8位二进制数的乘法程序

$ Start of Compile
#Tue Nov 07 08:49:38 2006

Synplicity Verilog Compiler, version 3.6t, Build 139R, built Jun 15 2006
Copyright (C) 1994-2006, Synplicity Inc.  All Rights Reserved

@E|Can't open file D:/Homework/ISE8.1
@END
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# Tue Nov 07 08:49:39 2006

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$ Start of Compile
#Tue Nov 07 08:49:44 2006

Synplicity Verilog Compiler, version 3.6t, Build 139R, built Jun 15 2006
Copyright (C) 1994-2006, Synplicity Inc.  All Rights Reserved

@E|Can't open file D:/Homework/ISE8.1
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Nov 07 08:49:44 2006

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$ Start of Compile
#Tue Nov 07 08:49:47 2006

Synplicity Verilog Compiler, version 3.6t, Build 139R, built Jun 15 2006
Copyright (C) 1994-2006, Synplicity Inc.  All Rights Reserved

@E|Can't open file D:/Homework/ISE8.1
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Nov 07 08:49:47 2006

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$ Start of Compile
#Tue Nov 07 08:49:50 2006

Synplicity Verilog Compiler, version 3.6t, Build 139R, built Jun 15 2006
Copyright (C) 1994-2006, Synplicity Inc.  All Rights Reserved

@E|Can't open file D:/Homework/ISE8.1
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Nov 07 08:49:50 2006

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$ Start of Compile
#Tue Nov 07 08:49:52 2006

Synplicity Verilog Compiler, version 3.6t, Build 139R, built Jun 15 2006
Copyright (C) 1994-2006, Synplicity Inc.  All Rights Reserved

@E|Can't open file D:/Homework/ISE8.1
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Nov 07 08:49:52 2006

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$ Start of Compile
#Tue Nov 07 20:32:51 2006

Synplicity Verilog Compiler, version 3.6t, Build 139R, built Jun 15 2006
Copyright (C) 1994-2006, Synplicity Inc.  All Rights Reserved

@E|Can't open file D:/Homework/ISE8.1
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Nov 07 20:32:52 2006

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$ Start of Compile
#Tue Nov 07 20:33:34 2006

Synplicity Verilog Compiler, version 3.6t, Build 139R, built Jun 15 2006
Copyright (C) 1994-2006, Synplicity Inc.  All Rights Reserved

@E|Can't open file D:/Homework/ISE8.1
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Nov 07 20:33:34 2006

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$ Start of Compile
#Tue Nov 07 20:33:40 2006

Synplicity Verilog Compiler, version 3.6t, Build 139R, built Jun 15 2006
Copyright (C) 1994-2006, Synplicity Inc.  All Rights Reserved

@E|Can't open file D:/Homework/ISE8.1
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Nov 07 20:33:40 2006

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$ Start of Compile
#Tue Nov 07 20:33:42 2006

Synplicity Verilog Compiler, version 3.6t, Build 139R, built Jun 15 2006
Copyright (C) 1994-2006, Synplicity Inc.  All Rights Reserved

@E|Can't open file D:/Homework/ISE8.1
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Nov 07 20:33:43 2006

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$ Start of Compile
#Tue Nov 07 20:33:46 2006

Synplicity Verilog Compiler, version 3.6t, Build 139R, built Jun 15 2006
Copyright (C) 1994-2006, Synplicity Inc.  All Rights Reserved

@E|Can't open file D:/Homework/ISE8.1
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Nov 07 20:33:46 2006

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$ Start of Compile
#Tue Nov 07 20:33:48 2006

Synplicity Verilog Compiler, version 3.6t, Build 139R, built Jun 15 2006
Copyright (C) 1994-2006, Synplicity Inc.  All Rights Reserved

@E|Can't open file D:/Homework/ISE8.1
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Nov 07 20:33:48 2006

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$ Start of Compile
#Tue Nov 07 20:33:50 2006

Synplicity Verilog Compiler, version 3.6t, Build 139R, built Jun 15 2006
Copyright (C) 1994-2006, Synplicity Inc.  All Rights Reserved

@E|Can't open file D:/Homework/ISE8.1
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Nov 07 20:33:50 2006

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$ Start of Compile
#Tue Nov 07 20:33:52 2006

Synplicity Verilog Compiler, version 3.6t, Build 139R, built Jun 15 2006
Copyright (C) 1994-2006, Synplicity Inc.  All Rights Reserved

@E|Can't open file D:/Homework/ISE8.1
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Nov 07 20:33:52 2006

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$ Start of Compile
#Tue Nov 07 20:34:36 2006

Synplicity Verilog Compiler, version 3.6t, Build 139R, built Jun 15 2006
Copyright (C) 1994-2006, Synplicity Inc.  All Rights Reserved

@I::"D:\Homework\ISE8.1 work\Mult\Mul.v"
Verilog syntax check successful!
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Nov 07 20:34:36 2006

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$ Start of Compile
#Tue Nov 07 20:35:05 2006

Synplicity Verilog Compiler, version 3.6t, Build 139R, built Jun 15 2006
Copyright (C) 1994-2006, Synplicity Inc.  All Rights Reserved

@I::"D:\Homework\ISE8.1 work\Mult\Mul.v"
Verilog syntax check successful!
Selecting top level module Mult
@N: CG364 :"D:\Homework\ISE8.1 work\Mult\Mul.v":21:7:21:10|Synthesizing module Mult

@N: CG179 :"D:\Homework\ISE8.1 work\Mult\Mul.v":35:17:35:19|Removing redundant assignment
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Nov 07 20:35:06 2006

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