clockdiv_tbw_par.prj

来自「本程序以XILINX公司的ISE８.２为开发平台」· PRJ 代码 · 共 4 行

verilog work "netgen/par/ClockDiv_timesim.v"
vhdl work "ClockDiv_tbw.vhw"
verilog work "C:/Xilinx/verilog/src/glbl.v"