_primary.vhd

来自「用VHDL写的运动计时表程序」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity time24 is
    port(
        cin             : in     vl_logic_vector(0 downto 0);
        clr             : in     vl_logic_vector(0 downto 0);
        load            : in     vl_logic_vector(0 downto 0);
        data            : in     vl_logic_vector(7 downto 0);
        \out\           : out    vl_logic_vector(7 downto 0)
    );
end time24;