代码搜索：Verilog
找到约 10,000 项符合「Verilog」的源代码
代码结果 10,000
www.eeworm.com/read/305630/13764313
txt 目录.txt
目 录
译者序
前言
第1章 简介 1
1.1 什么是Verilog HDL？ 1
1.2 历史 1
1.3 主要能力 1
第2章 HDL指南 4
2.1 模块 4
2.2 时延 5
2.3 数据流描述方式 5
2.4 行为描述方式 6
2.5 结构化描述形式 8
2.6 混合设计描述方式 9
2.7 设计模拟
www.eeworm.com/read/304723/13788199
smsg test.map.smsg
Warning (10268): Verilog HDL information at shift_reg.v(26): Always Construct contains both blocking and non-blocking assignments
www.eeworm.com/read/151353/5683665
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity global is
port(
\out\ : out vl_logic
);
end global;
www.eeworm.com/read/146593/5736618
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity m3s005br is
port(
clk : in vl_logic;
nrst : in vl_logic;
a : in vl_logic_
www.eeworm.com/read/146593/5736625
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity m3s006br is
port(
clk : in vl_logic;
nrst : in vl_logic;
clkenab : in vl_logic;
www.eeworm.com/read/146593/5736627
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity m3s002br is
port(
clk : in vl_logic;
nrst : in vl_logic;
clkenab : in vl_logic;
www.eeworm.com/read/146593/5736629
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity m3s003br is
port(
clk : in vl_logic;
nrst : in vl_logic;
clkenab : in vl_logic;
www.eeworm.com/read/146593/5736631
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity m3s001br is
port(
clk : in vl_logic;
nrst : in vl_logic;
clkenab : in vl_logic;
www.eeworm.com/read/141343/5770088
ads grt-vcd.ads
-- GHDL Run Time (GRT) - VCD generator.
-- Copyright (C) 2002, 2003, 2004, 2005 Tristan Gingold
--
-- GHDL is free software; you can redistribute it and/or modify it under
-- the terms of the GNU
www.eeworm.com/read/109657/6173168
txt edit_mpf.txt
*****Copy the following line to the [vsim] section of your simulation.mpf.*****
Veriuser = $MG_LIB/mti_modelsim_verilog/libmgmm.so