代码搜索：Verilog
找到约 10,000 项符合「Verilog」的源代码
代码结果 10,000
www.eeworm.com/read/461671/1551830
make_verilog
verilog \
../../../bench/verilog/oc8051_tb.v \
../../../bench/verilog/oc8051_xram.v \
../../../bench/verilog/oc8051_uart_test.v \
../../../bench/verilog/oc8051_xrom.v \
../../../r
www.eeworm.com/read/233075/4694732
v verilog.v
// generated by newgenasym Fri Mar 16 13:12:38 2001
module bnc_conn (agnd1, agnd2, agnd3, agnd4, center);
inout agnd1;
inout agnd2;
inout agnd3;
inout agnd4;
inout center;
www.eeworm.com/read/233075/4694743
v verilog.v
// generated by newgenasym Fri Mar 16 13:33:15 2001
module inductor (a, b);
inout a;
inout b;
initial
begin
end
endmodule
www.eeworm.com/read/233075/4694753
v verilog.v
// generated by newgenasym Fri Mar 16 11:48:43 2001
module res (a, b);
inout a;
inout b;
initial
begin
end
endmodule
www.eeworm.com/read/233075/4694763
v verilog.v
// generated by newgenasym Thu Mar 22 14:14:15 2001
module \20l10 (i1, i10, i11, i12, i2, i3, i4, i5, i6, i7, i8, i9, o1, o10, o2, o3,
o4, o5, o6, o7, o8, o9);
input i1;
input i10;
www.eeworm.com/read/233075/4694772
v verilog.v
// generated by newgenasym Thu Mar 22 14:40:16 2001
module tc55b4257 (a0, a1, a10, a11, a12, a13, a14, a15, a16, a17, a2, a3, a4, a5, a6,
a7, a8, a9, \ce* , dq1, dq2, dq3, dq4, \eo* , io1,
www.eeworm.com/read/233075/4694781
v verilog.v
// generated by newgenasym Thu Mar 22 14:41:46 2001
module tlc5602 (agnd1, aout, avcc1, avcc2, clk, comp, d0, d1, d2, d3, d4, d5, d6,
d7, gnd1, nc1, nc2, ref, vcc1, vcc2);
inout agnd1;
www.eeworm.com/read/233075/4694790
v verilog.v
// generated by newgenasym Thu Mar 22 14:21:06 2001
module conn64 (a);
inout [64:1] a;
initial
begin
end
endmodule
www.eeworm.com/read/233075/4694799
v verilog.v
// generated by newgenasym Thu Mar 22 14:30:42 2001
module fct16245 (a, b, dir, \g* );
input [7:0] a;
inout [7:0] b;
input dir;
input \g* ;
initial
begin
end
www.eeworm.com/read/233075/4694808
v verilog.v
// generated by newgenasym Thu Mar 22 14:24:25 2001
module epc1064 (\cs* , data, dclk, oe);
input \cs* ;
output data;
input dclk;
input oe;
initial
begin
end