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VHDL 的代码
muladdsgn.vhd
-------------------------------------------------------------------------------
-- Title : Signed multiplier-adder
-- Project : VHDL Library of Arithmetic Units
-----------------------------
allzerodet.vhd
-------------------------------------------------------------------------------
-- Title : All-zeroes detector
-- Project : VHDL Library of Arithmetic Units
---------------------------------
add.vhd
-------------------------------------------------------------------------------
-- Title : Parallel-prefix adder
-- Project : VHDL Library of Arithmetic Units
-------------------------------
example.vhd
-------------------------------------------------------------------------------
-- Title : Example instantiation of an arithmetic unit
-- Project : VHDL Library of Arithmetic Units
---------
addmulsgn.vhd
-------------------------------------------------------------------------------
-- Title : Signed adder-multiplier
-- Project : VHDL Library of Arithmetic Units
-----------------------------
prefixor.vhd
-------------------------------------------------------------------------------
-- Title : Parallel-prefix OR structure
-- Project : VHDL Library of Arithmetic Units
------------------------
inc.vhd
-------------------------------------------------------------------------------
-- Title : Parallel-prefix incrementer
-- Project : VHDL Library of Arithmetic Units
-------------------------
example.proj
set search_path " \
. \
./vhdl \
./hdl \
./sl \
./sldb \
$SYNOPSYS/librari
example.proj
set search_path " \
. \
./vhdl \
./hdl \
./sl \
./sldb \
$SYNOPSYS/librari
bin2gray.vhd
-------------------------------------------------------------------------------
-- Title : Binary-to-Gray converter
-- Project : VHDL Library of Arithmetic Units
----------------------------