allzerodet.vhd

来自「Cadence的VHDL运算库包」· VHDL 代码 · 共 67 行

-------------------------------------------------------------------------------
-- Title       : All-zeroes detector
-- Project     : VHDL Library of Arithmetic Units
-------------------------------------------------------------------------------
-- File        : AllZeroDet.vhd
-- Author      : Reto Zimmermann  <[e-mail]>
-- Company     : Integrated Systems Laboratory, ETH Zurich
-- Date        : 1997/12/29
-------------------------------------------------------------------------------
-- Copyright (c) 1998 Integrated Systems Laboratory, ETH Zurich
-------------------------------------------------------------------------------
-- Description :
-- Detection of the all-zeroes vector.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library arith_lib;
use arith_lib.arith_lib.all;

-------------------------------------------------------------------------------

entity AllZeroDet is

  generic (width : positive := 8);  	-- word width

  port (A : in std_logic_vector(width-1 downto 0);  -- operand
	Z : out std_logic);		-- all-zeroes flag

end AllZeroDet;

-------------------------------------------------------------------------------

architecture Behavioral of AllZeroDet is

  signal Zeroes : std_logic_vector(width-1 downto 0);  -- zeroes vector

begin

  -- initialization of zeroes vector
  Zeroes <= (others => '0');

  -- all-zeroes detection
  Z <= '1' when A = Zeroes else '0';

end Behavioral;

-------------------------------------------------------------------------------

architecture Structural of AllZeroDet is

  signal ZT : std_logic;  -- temp.

begin

  -- all-zeroes detection
  zeroFlag : RedOr
    generic map (width)
    port map (A, ZT);

  -- result
  Z <= not ZT;

end Structural;

-------------------------------------------------------------------------------