example.vhd

来自「Cadence的VHDL运算库包」· VHDL 代码 · 共 47 行

-------------------------------------------------------------------------------
-- Title       : Example instantiation of an arithmetic unit
-- Project     : VHDL Library of Arithmetic Units
-------------------------------------------------------------------------------
-- File        : Example.vhd
-- Author      : Reto Zimmermann  <[e-mail]>
-- Company     : Integrated Systems Laboratory, ETH Zurich
-- Date        : 1997/11/04
-------------------------------------------------------------------------------
-- Copyright (c) 1998 Integrated Systems Laboratory, ETH Zurich
-------------------------------------------------------------------------------
-- Description :
-- Example instantiation of an arithmetic unit. The component declaration can
-- be omitted because it is included in the `arith_lib' package.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library arith_lib;
use arith_lib.arith_lib.all;

-------------------------------------------------------------------------------

entity Example is

  generic (width : positive := 8);  	-- word width
  
  port (A, B : in std_logic_vector(width-1 downto 0);  -- operands
	S : out std_logic_vector(width-1 downto 0));  -- result

end Example;

-------------------------------------------------------------------------------

architecture Structural of Example is

begin

  -- instantiation of adder with fast architecture
  adder : Add
    generic map (width, fast)
    port map (A, B, S);

end Structural;

-------------------------------------------------------------------------------