add.vhd

来自「Cadence的VHDL运算库包」· VHDL 代码 · 共 102 行

-------------------------------------------------------------------------------
-- Title       : Parallel-prefix adder
-- Project     : VHDL Library of Arithmetic Units
-------------------------------------------------------------------------------
-- File        : Add.vhd
-- Author      : Reto Zimmermann  <[e-mail]>
-- Company     : Integrated Systems Laboratory, ETH Zurich
-- Date        : 1997/11/04
-------------------------------------------------------------------------------
-- Copyright (c) 1998 Integrated Systems Laboratory, ETH Zurich
-------------------------------------------------------------------------------
-- Description :
-- Binary adder using parallel-prefix carry-lookahead logic.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library synergy;  use synergy.signed_arith.all;
library arith_lib;
use arith_lib.arith_lib.all;

-------------------------------------------------------------------------------

entity Add is

  generic (width : positive := 8;  	-- word width
	   speed : speedType := fast);  -- performance parameter

  port (A, B : in std_logic_vector(width-1 downto 0);  -- operands
	S : out std_logic_vector(width-1 downto 0));  -- sum

end Add;

-------------------------------------------------------------------------------

architecture Behavioral of Add is

  signal Auns, Buns, Suns : unsigned(width-1 downto 0);  -- unsigned

begin

  -- type conversion: std_logic_vector -> unsigned
  Auns <= unsigned(A);
  Buns <= unsigned(B);

  -- addition
  Suns <= Auns + Buns;

  -- type conversion: unsigned -> std_logic_vector
  S <= std_logic_vector(Suns);

end Behavioral;

-------------------------------------------------------------------------------

architecture Structural of Add is 

  signal GI, PI : std_logic_vector(width-1 downto 0);  -- prefix gen./prop. in
  signal GO, PO : std_logic_vector(width-1 downto 0);  -- prefix gen./prop. out
  signal PT : std_logic_vector(width-1 downto 0);  -- adder propagate temp
  signal Auns, Buns, Suns : unsigned(width-1 downto 0);  -- unsigned

begin

  -- default ripple-carry adder as slow implementation
  addSlow : if speed = slow generate

    -- type conversion: std_logic_vector -> unsigned
    Auns <= unsigned(A);
    Buns <= unsigned(B);

    -- addition
    Suns <= Auns + Buns;

    -- type conversion: unsigned -> std_logic_vector
    S <= std_logic_vector(Suns);

  end generate addSlow;

  -- parallel-prefix adders as medium and fast implementations
  addFast : if speed /= slow generate

    -- calculate prefix input generate/propagate signals
    GI <= A and B;
    PI <= A or B;
    -- calculate adder propagate signals (PT = A xor B)
    PT <= not GI and PI;

    -- calculate prefix output generate/propagate signals
    prefix : PrefixAndOr
      generic map (width, speed)
      port map (GI, PI, GO, PO);

    -- calculate sum bits
    S <= PT xor GO(width-2 downto 0) & '0';

  end generate addFast;

end Structural;

-------------------------------------------------------------------------------