muladdsgn.vhd

Cadence的VHDL运算库包

-------------------------------------------------------------------------------
-- Title       : Signed multiplier-adder
-- Project     : VHDL Library of Arithmetic Units
-------------------------------------------------------------------------------
-- File        : MulAddSgn.vhd
-- Author      : Reto Zimmermann  <[e-mail]>
-- Company     : Integrated Systems Laboratory, ETH Zurich
-- Date        : 1997/12/02
-------------------------------------------------------------------------------
-- Copyright (c) 1998 Integrated Systems Laboratory, ETH Zurich
-------------------------------------------------------------------------------
-- Description :
-- Multiplier-adder for signed numbers (Baugh-Wooley). First multiplies two
-- numbers, then adds an additional operand to the result.
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library synergy;  use synergy.signed_arith.all;
library arith_lib;
use arith_lib.arith_lib.all;

-------------------------------------------------------------------------------

entity MulAddSgn is

  generic (widthX : positive := 8;	-- word width of XS, XC (<= widthY)
	   widthY : positive := 8;	-- word width of Y
	   widthA : positive := 20;	-- word width of A (>= widthX+widthY)
	   speed : speedType := fast);	-- performance parameter

  port (X : in std_logic_vector(widthX-1 downto 0);  -- multiplier
	Y : in std_logic_vector(widthY-1 downto 0);  -- multiplicand
	A : in std_logic_vector(widthA-1 downto 0);  -- augend
        P : out std_logic_vector(widthA-1 downto 0));  -- product

end MulAddSgn;

-------------------------------------------------------------------------------

architecture Behavioral of MulAddSgn is

  signal Xuns : signed(widthX-1 downto 0);  -- signed
  signal Yuns : signed(widthY-1 downto 0);  -- signed
  signal Auns : signed(widthA-1 downto 0);  -- signed
  signal Puns : signed(widthA-1 downto 0);  -- signed

begin

  -- type conversion: std_logic_vector -> signed
  Xuns <= signed(X);
  Yuns <= signed(Y);
  Auns <= signed(A);

  -- multiplication and addition
  Puns <= (Xuns * Yuns) + Auns;

  -- type conversion: signed -> std_logic_vector
  P <= std_logic_vector(Puns);

end Behavioral;

-------------------------------------------------------------------------------

architecture Structural of MulAddSgn is 

						-- partial products
  signal PP : std_logic_vector((widthX+2)*(widthX+widthY)-1 downto 0);
						-- intermediate sum/carry bits
  signal ST1, CT1, ST2, CT2 : std_logic_vector(widthA-1 downto 0); 

begin

  -- generation of partial products
  ppGen : MulPPGenSgn
    generic map (widthX, widthY)
    port map (X, Y, PP);

  -- carry-save addition of partial products
  csvAdd1 : AddMopCsv
    generic map (widthX+widthY, widthX+2, speed)
    port map (PP, ST1(widthX+widthY-1 downto 0),
	      CT1(widthX+widthY-1 downto 0));

  -- extend
  extend : if widthA > widthX+widthY generate
    ST1(widthX+widthY) <= not ST1(widthX+widthY-1);
--synopsys_bug    ST1(widthA-1 downto widthX+widthY+1) <= (others => '0');
    synopsys_bug1 : for i in widthA-1 downto widthX+widthY+1 generate
      ST1(i) <= '0';
    end generate synopsys_bug1;
--synopsys_bug    CT1(widthA-1 downto widthX+widthY) <= (others => '1');
    synopsys_bug2 : for i in widthA-1 downto widthX+widthY generate
      CT1(i) <= '1';
    end generate synopsys_bug2;
  end generate extend;

  -- carry-save addition of augend
  csvAdd2 : AddCsv
    generic map (widthA)
    port map (A, CT1, ST1, ST2, CT2);

  -- final carry-propagate addition
  cpAdd : Add
    generic map (widthA, speed)
    port map (ST2, CT2, P);

end Structural;

-------------------------------------------------------------------------------