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core51.prj
KEY LIBERO "6.0.0.133"
KEY HDLTechnology "VHDL"
KEY VendorTechnology "Actel PA,APA075,100 TQFP Technology"
KEY SimulationType "VHDL"
KEY Vendor "Actel"
KEY ActiveRoot "addsub_cy"
LIST REVISIONS
core51.prj
KEY LIBERO "6.0.0.133"
KEY HDLTechnology "VHDL"
KEY VendorTechnology "Actel PA,APA075,100 TQFP Technology"
KEY SimulationType "VHDL"
KEY Vendor "Actel"
KEY ActiveRoot "addsub_cy"
LIST REVISIONS
b.timesim_vhw
-- F:\VHDL\SHUZIZHONG\SHUZIZHONG
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Sun Dec 07 12:11:06 2008
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your
cc.timesim_vhw
-- F:\VHDL\SHUZIZHONG\SHUZIZHONG
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Sun Dec 07 12:12:41 2008
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your
a.vhw
-- F:\VHDL\SHUZIZHONG\SHUZIZHONG
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Sun Dec 07 11:28:48 2008
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your
e.vhw
-- F:\VHDL\SHUZIZHONG\SHUZIZHONG
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Sun Dec 07 12:44:06 2008
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your
dd.vhw
-- F:\VHDL\SHUZIZHONG\SHUZIZHONG
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Sun Dec 07 12:31:53 2008
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your
b.vhw
-- F:\VHDL\SHUZIZHONG\SHUZIZHONG
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Sun Dec 07 11:36:11 2008
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your
c.vhw
-- F:\VHDL\SHUZIZHONG\SHUZIZHONG
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Sun Dec 07 12:35:19 2008
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your
cc.vhw
-- F:\VHDL\SHUZIZHONG\SHUZIZHONG
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Sun Dec 07 12:54:03 2008
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your