e.vhw

EDA课程设计（带完整设计报告）

-- F:\VHDL\SHUZIZHONG\SHUZIZHONG
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Sun Dec 07 12:44:06 2008
-- 
-- Notes:
-- 1) This testbench has been automatically generated from
--   your Test Bench Waveform
-- 2) To use this as a user modifiable testbench do the following:
--   - Save it as a file with a .vhd extension (i.e. File->Save As...)
--   - Add it to your project as a testbench source (i.e. Project->Add Source...)
-- 

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY e IS
END e;

ARCHITECTURE testbench_arch OF e IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
	COMPONENT yima
		PORT (
			sec1 : In  std_logic_vector (3 DOWNTO 0);
			sec2 : In  std_logic_vector (3 DOWNTO 0);
			min1 : In  std_logic_vector (3 DOWNTO 0);
			min2 : In  std_logic_vector (3 DOWNTO 0);
			hour1 : In  std_logic_vector (3 DOWNTO 0);
			hour2 : In  std_logic_vector (3 DOWNTO 0);
			s1 : Out  std_logic_vector (6 DOWNTO 0);
			s2 : Out  std_logic_vector (6 DOWNTO 0);
			m1 : Out  std_logic_vector (6 DOWNTO 0);
			m2 : Out  std_logic_vector (6 DOWNTO 0);
			h1 : Out  std_logic_vector (6 DOWNTO 0);
			h2 : Out  std_logic_vector (6 DOWNTO 0)
		);
	END COMPONENT;

	SIGNAL sec1 : std_logic_vector (3 DOWNTO 0);
	SIGNAL sec2 : std_logic_vector (3 DOWNTO 0);
	SIGNAL min1 : std_logic_vector (3 DOWNTO 0);
	SIGNAL min2 : std_logic_vector (3 DOWNTO 0);
	SIGNAL hour1 : std_logic_vector (3 DOWNTO 0);
	SIGNAL hour2 : std_logic_vector (3 DOWNTO 0);
	SIGNAL s1 : std_logic_vector (6 DOWNTO 0);
	SIGNAL s2 : std_logic_vector (6 DOWNTO 0);
	SIGNAL m1 : std_logic_vector (6 DOWNTO 0);
	SIGNAL m2 : std_logic_vector (6 DOWNTO 0);
	SIGNAL h1 : std_logic_vector (6 DOWNTO 0);
	SIGNAL h2 : std_logic_vector (6 DOWNTO 0);

BEGIN
	UUT : yima
	PORT MAP (
		sec1 => sec1,
		sec2 => sec2,
		min1 => min1,
		min2 => min2,
		hour1 => hour1,
		hour2 => hour2,
		s1 => s1,
		s2 => s2,
		m1 => m1,
		m2 => m2,
		h1 => h1,
		h2 => h2
	);

	PROCESS
		VARIABLE TX_OUT : LINE;
		VARIABLE TX_ERROR : INTEGER := 0;

		PROCEDURE CHECK_s1(
			next_s1 : std_logic_vector (6 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (s1 /= next_s1) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns s1="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, s1);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_s1);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_s2(
			next_s2 : std_logic_vector (6 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (s2 /= next_s2) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns s2="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, s2);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_s2);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_m1(
			next_m1 : std_logic_vector (6 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (m1 /= next_m1) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns m1="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, m1);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_m1);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_m2(
			next_m2 : std_logic_vector (6 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (m2 /= next_m2) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns m2="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, m2);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_m2);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_h1(
			next_h1 : std_logic_vector (6 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (h1 /= next_h1) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns h1="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, h1);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_h1);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_h2(
			next_h2 : std_logic_vector (6 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (h2 /= next_h2) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns h2="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, h2);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_h2);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		BEGIN
		-- --------------------
		sec1 <= transport std_logic_vector'("0000"); --0
		sec2 <= transport std_logic_vector'("0000"); --0
		min1 <= transport std_logic_vector'("0000"); --0
		min2 <= transport std_logic_vector'("0000"); --0
		hour1 <= transport std_logic_vector'("0000"); --0
		hour2 <= transport std_logic_vector'("0000"); --0
		-- --------------------
		WAIT FOR 100 ns; -- Time=100 ns
		sec1 <= transport std_logic_vector'("0001"); --1
		sec2 <= transport std_logic_vector'("0001"); --1
		min1 <= transport std_logic_vector'("0001"); --1
		min2 <= transport std_logic_vector'("0001"); --1
		hour1 <= transport std_logic_vector'("0001"); --1
		hour2 <= transport std_logic_vector'("0001"); --1
		-- --------------------
		WAIT FOR 100 ns; -- Time=200 ns
		sec1 <= transport std_logic_vector'("0010"); --2
		sec2 <= transport std_logic_vector'("0010"); --2
		min1 <= transport std_logic_vector'("0010"); --2
		min2 <= transport std_logic_vector'("0010"); --2
		hour1 <= transport std_logic_vector'("0010"); --2
		hour2 <= transport std_logic_vector'("0010"); --2
		-- --------------------
		WAIT FOR 100 ns; -- Time=300 ns
		sec1 <= transport std_logic_vector'("0011"); --3
		sec2 <= transport std_logic_vector'("0011"); --3
		min1 <= transport std_logic_vector'("0011"); --3
		min2 <= transport std_logic_vector'("0011"); --3
		hour1 <= transport std_logic_vector'("0011"); --3
		hour2 <= transport std_logic_vector'("0011"); --3
		-- --------------------
		WAIT FOR 100 ns; -- Time=400 ns
		sec1 <= transport std_logic_vector'("0100"); --4
		sec2 <= transport std_logic_vector'("0100"); --4
		min1 <= transport std_logic_vector'("0100"); --4
		min2 <= transport std_logic_vector'("0100"); --4
		hour1 <= transport std_logic_vector'("0100"); --4
		hour2 <= transport std_logic_vector'("0100"); --4
		-- --------------------
		WAIT FOR 100 ns; -- Time=500 ns
		sec1 <= transport std_logic_vector'("0110"); --6
		sec2 <= transport std_logic_vector'("0110"); --6
		min1 <= transport std_logic_vector'("0110"); --6
		min2 <= transport std_logic_vector'("0110"); --6
		hour1 <= transport std_logic_vector'("0110"); --6
		hour2 <= transport std_logic_vector'("0110"); --6
		-- --------------------
		WAIT FOR 100 ns; -- Time=600 ns
		sec1 <= transport std_logic_vector'("0111"); --7
		sec2 <= transport std_logic_vector'("0111"); --7
		min1 <= transport std_logic_vector'("0111"); --7
		min2 <= transport std_logic_vector'("0111"); --7
		hour1 <= transport std_logic_vector'("0111"); --7
		hour2 <= transport std_logic_vector'("0111"); --7
		-- --------------------
		WAIT FOR 100 ns; -- Time=700 ns
		sec1 <= transport std_logic_vector'("1000"); --8
		sec2 <= transport std_logic_vector'("1000"); --8
		min1 <= transport std_logic_vector'("1000"); --8
		min2 <= transport std_logic_vector'("1000"); --8
		hour1 <= transport std_logic_vector'("1000"); --8
		hour2 <= transport std_logic_vector'("1000"); --8
		-- --------------------
		WAIT FOR 100 ns; -- Time=800 ns
		sec1 <= transport std_logic_vector'("1001"); --9
		sec2 <= transport std_logic_vector'("1001"); --9
		min1 <= transport std_logic_vector'("1001"); --9
		min2 <= transport std_logic_vector'("1001"); --9
		hour1 <= transport std_logic_vector'("1001"); --9
		hour2 <= transport std_logic_vector'("1001"); --9
		-- --------------------
		WAIT FOR 2500 ns; -- Time=3300 ns
		-- --------------------

		IF (TX_ERROR = 0) THEN 
			STD.TEXTIO.write(TX_OUT,string'("No errors or warnings"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Simulation successful (not a failure).  No problems detected. "
				SEVERITY FAILURE;
		ELSE
			STD.TEXTIO.write(TX_OUT, TX_ERROR);
			STD.TEXTIO.write(TX_OUT, string'(
				" errors found in simulation"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Errors found during simulation"
				SEVERITY FAILURE;
		END IF;
	END PROCESS;
END testbench_arch;

CONFIGURATION yima_cfg OF e IS
	FOR testbench_arch
	END FOR;
END yima_cfg;