dd.vhw

EDA课程设计（带完整设计报告）

-- F:\VHDL\SHUZIZHONG\SHUZIZHONG
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Sun Dec 07 12:31:53 2008
-- 
-- Notes:
-- 1) This testbench has been automatically generated from
--   your Test Bench Waveform
-- 2) To use this as a user modifiable testbench do the following:
--   - Save it as a file with a .vhd extension (i.e. File->Save As...)
--   - Add it to your project as a testbench source (i.e. Project->Add Source...)
-- 

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY dd IS
END dd;

ARCHITECTURE testbench_arch OF dd IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
	COMPONENT alarm1
		PORT (
			reset : In  std_logic;
			Min1 : In  std_logic_vector (3 DOWNTO 0);
			min2 : In  std_logic_vector (3 DOWNTO 0);
			Alarm : Out  std_logic
		);
	END COMPONENT;

	SIGNAL reset : std_logic;
	SIGNAL Min1 : std_logic_vector (3 DOWNTO 0);
	SIGNAL min2 : std_logic_vector (3 DOWNTO 0);
	SIGNAL Alarm : std_logic;

BEGIN
	UUT : alarm1
	PORT MAP (
		reset => reset,
		Min1 => Min1,
		min2 => min2,
		Alarm => Alarm
	);

	PROCESS
		VARIABLE TX_OUT : LINE;
		VARIABLE TX_ERROR : INTEGER := 0;

		PROCEDURE CHECK_Alarm(
			next_Alarm : std_logic;
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (Alarm /= next_Alarm) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns Alarm="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, Alarm);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_Alarm);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		BEGIN
		-- --------------------
		reset <= transport '1';
		Min1 <= transport std_logic_vector'("0001"); --1
		min2 <= transport std_logic_vector'("0000"); --0
		-- --------------------
		WAIT FOR 200 ns; -- Time=200 ns
		Min1 <= transport std_logic_vector'("0101"); --5
		min2 <= transport std_logic_vector'("0000"); --0
		-- --------------------
		WAIT FOR 200 ns; -- Time=400 ns
		Min1 <= transport std_logic_vector'("0101"); --5
		min2 <= transport std_logic_vector'("0000"); --0
		-- --------------------
		WAIT FOR 200 ns; -- Time=600 ns
		Min1 <= transport std_logic_vector'("0000"); --0
		min2 <= transport std_logic_vector'("0000"); --0
		-- --------------------
		WAIT FOR 1500 ns; -- Time=2100 ns
		-- --------------------

		IF (TX_ERROR = 0) THEN 
			STD.TEXTIO.write(TX_OUT,string'("No errors or warnings"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Simulation successful (not a failure).  No problems detected. "
				SEVERITY FAILURE;
		ELSE
			STD.TEXTIO.write(TX_OUT, TX_ERROR);
			STD.TEXTIO.write(TX_OUT, string'(
				" errors found in simulation"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Errors found during simulation"
				SEVERITY FAILURE;
		END IF;
	END PROCESS;
END testbench_arch;

CONFIGURATION alarm1_cfg OF dd IS
	FOR testbench_arch
	END FOR;
END alarm1_cfg;