core51.prj

VHDL写的51单片机内核

KEY LIBERO "6.0.0.133"
KEY HDLTechnology "VHDL"
KEY VendorTechnology "Actel PA,APA075,100 TQFP Technology"
KEY SimulationType "VHDL"
KEY Vendor "Actel"
KEY ActiveRoot "addsub_cy"
LIST REVISIONS
VALUE="Impl1",NUM=1
CURREV=1
ENDLIST
LIST BlockViewMap
ENDLIST
LIST BlockSymbols
ENDLIST
LIST Schematics
ENDLIST
LIST HDLFiles
VALUE "hdl\addsub_core_.vhd"
VALUE "hdl\addsub_core_struc.vhd"
VALUE "hdl\addsub_core_struc_cfg.vhd"
VALUE "hdl\addsub_cy_.vhd"
VALUE "hdl\addsub_cy_rtl.vhd"
VALUE "hdl\addsub_cy_rtl_cfg.vhd"
VALUE "hdl\addsub_ovcy_.vhd"
VALUE "hdl\addsub_ovcy_rtl.vhd"
VALUE "hdl\addsub_ovcy_rtl_cfg.vhd"
VALUE "hdl\alucore_.vhd"
VALUE "hdl\alucore_rtl.vhd"
VALUE "hdl\alucore_rtl_cfg.vhd"
VALUE "hdl\alumux_.vhd"
VALUE "hdl\alumux_rtl.vhd"
VALUE "hdl\alumux_rtl_cfg.vhd"
VALUE "hdl\comb_divider_.vhd"
VALUE "hdl\comb_divider_rtl.vhd"
VALUE "hdl\comb_divider_rtl_cfg.vhd"
VALUE "hdl\comb_mltplr_.vhd"
VALUE "hdl\comb_mltplr_rtl.vhd"
VALUE "hdl\comb_mltplr_rtl_cfg.vhd"
VALUE "hdl\control_fsm_.vhd"
VALUE "hdl\control_fsm_rtl.vhd"
VALUE "hdl\control_fsm_rtl_cfg.vhd"
VALUE "hdl\control_mem_.vhd"
VALUE "hdl\control_mem_rtl.vhd"
VALUE "hdl\control_mem_rtl_cfg.vhd"
VALUE "hdl\dcml_adjust_.vhd"
VALUE "hdl\dcml_adjust_rtl.vhd"
VALUE "hdl\dcml_adjust_rtl_cfg.vhd"
VALUE "hdl\mc8051_alu_.vhd"
VALUE "hdl\mc8051_alu_struc.vhd"
VALUE "hdl\mc8051_alu_struc_cfg.vhd"
VALUE "hdl\mc8051_control_.vhd"
VALUE "hdl\mc8051_control_struc.vhd"
VALUE "hdl\mc8051_control_struc_cfg.vhd"
VALUE "hdl\mc8051_core_.vhd"
VALUE "hdl\mc8051_core_struc.vhd"
VALUE "hdl\mc8051_core_struc_cfg.vhd"
VALUE "hdl\mc8051_p.vhd"
VALUE "hdl\mc8051_siu_.vhd"
VALUE "hdl\mc8051_siu_rtl.vhd"
VALUE "hdl\mc8051_siu_rtl_cfg.vhd"
VALUE "hdl\mc8051_tmrctr_.vhd"
VALUE "hdl\mc8051_tmrctr_rtl.vhd"
VALUE "hdl\mc8051_tmrctr_rtl_cfg.vhd"
VALUE "hdl\mc8051_top_.vhd"
VALUE "hdl\mc8051_top_struc.vhd"
VALUE "hdl\mc8051_top_struc_cfg.vhd"
ENDLIST
LIST PackageFiles
ENDLIST
LIST GENFiles
ENDLIST
LIST SynthesisFiles
ENDLIST
LIST PhySynthesisFiles
ENDLIST
LIST StimulusFiles
ENDLIST
LIST ConstraintFiles
ENDLIST
LIST RecentFile
ENDLIST
LIST StimulusAssociation
ENDLIST
LIST SimulationOptions
UseAutomaticDoFile=TRUE
CompilePackage=TRUE
IncludeWaveDo=FALSE
Type=max
RunTime=1000ns
Resolution=1ps
VsimOpt=
EntityName=testbench
TopInstanceName=<top>_0
DoFileName=
DoFileName2=wave.do
Profile=ModelSim 5.8b
Tool=ModelSim 5.8b
Location=C:\Libero\Model\win32acoem\modelsim.exe
AdditionalParameter=
ENDLIST
LIST StimulusOptions
Profile=WFL 9.0u
Tool=WFL 9.0u
Location=C:\Libero\WFL\bin\syncad.exe
AdditionalParameter=-pwflite
ENDLIST
LIST SynthesisOptions
Profile=Synplify 7.5.1A
Tool=Synplify 7.5.1A
Location=C:\Program Files\synplicity\Synplify_75\bin\synplify.exe
AdditionalParameter=
ENDLIST
LIST PhySynthesisOptions
Profile=PALACE 1.2
Tool=PALACE 1.2
Location=C:\Libero\PALACE\bin\palace_actel.exe
AdditionalParameter=
ENDLIST
LIST ProjectState5.1
ENDLIST
LIST ExcludePackageForSimulation
ENDLIST
LIST ExcludePackageForSynthesis
ENDLIST
LIST IncludeModuleForSimulation
ENDLIST
LIST OODAdbs
ENDLIST