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VHDL 的代码
can_top.vhdsim_xlate
can_top.vhdsim_xlate -- generated only for ProjNav status tracking
Simulation Model Target: Generic_VHDL
fct807.vhd
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-- File Name: fct807.vhd
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-- Copyrigh
cy2309nz.vhd
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-- File Name: cy2309nz.vhd
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-- Copyri
hwtb_ddr1_top.prj
###############################################################################
## Copyright (c) 2006 Xilinx, Inc.
## This design is confidential and proprietary of Xilinx, All Rights Reserved.
###
tennis.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any
dds_modelsim.xrf
vendor_name = ModelSim
source_file = 1, D:/cwdds/REG10B.VHD
source_file = 1, D:/cwdds/lpm_rom0.vhd
source_file = 1, D:/cwdds/DDS_VHDL.vhd
source_file = 1, D:/cwdds/ADDER10B.VHD
source_file = 1, e
dds.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info:
dds.fit.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartu
light.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus II " "Info: Runni
speaker.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any