fct807.vhd

Vhdl cod for a clock for sp3e

--------------------------------------------------------------------------------
--  File Name: fct807.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 2001-2003 Free Model Foundry; http://www.FreeModelFoundry.com/
-- 
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
-- 
--  MODIFICATION HISTORY:
-- 
--  version | author  | mod date | changes made
--    V1.0  R. Munden  01 FEB 16  Initial release
--    V2.0  R. Munden  03 JAN 22  Flattened model to match customer usage
--------------------------------------------------------------------------------
--  PART DESCRIPTION:
-- 
--  Library:     CLOCK
--  Technology:  CMOS
--  Part:        FCT807
-- 
--  Description:  1 to 10 Clock Driver
--------------------------------------------------------------------------------

LIBRARY IEEE;    USE IEEE.std_logic_1164.ALL;
                 USE IEEE.VITAL_timing.ALL;
                 USE IEEE.VITAL_primitives.ALL;
LIBRARY FMF;     USE FMF.gen_utils.ALL;

--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY fct807 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_A              : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays
        tpd_A_Y1         : VitalDelayType01 := UnitDelay01;
        -- generic control parameters
        MsgOn               : BOOLEAN  := DefaultMsgOn;
        XOn                 : Boolean  := DefaultXOn;
        InstancePath        : STRING   := DefaultInstancePath;
        -- For FMF SDF techonology file usage
        TimingModel         : STRING   := DefaultTimingModel
    );
    PORT (
        A           : IN    std_ulogic := 'U';
        Y1          : OUT   std_ulogic := 'U';
        Y2          : OUT   std_ulogic := 'U';
        Y3          : OUT   std_ulogic := 'U';
        Y4          : OUT   std_ulogic := 'U';
        Y5          : OUT   std_ulogic := 'U';
        Y6          : OUT   std_ulogic := 'U';
        Y7          : OUT   std_ulogic := 'U';
        Y8          : OUT   std_ulogic := 'U';
        Y9          : OUT   std_ulogic := 'U';
        Y10         : OUT   std_ulogic := 'U'
    );
    ATTRIBUTE VITAL_LEVEL0 of fct807 : ENTITY IS TRUE;
END fct807;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of fct807 IS
    ATTRIBUTE VITAL_LEVEL1 of vhdl_behavioral : ARCHITECTURE IS TRUE;

    CONSTANT partID     : STRING := "FCT807";

    SIGNAL A_ipd        : std_ulogic := 'U';
    SIGNAL Y            : std_ulogic := 'U';

BEGIN
    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1: VitalWireDelay (A_ipd, A, tipd_A);

    END BLOCK;

    ----------------------------------------------------------------------------
    -- Concurrent procedure calls
    ----------------------------------------------------------------------------
    a_1 : VitalBuf (q => Y1, a => Y);
    a_2 : VitalBuf (q => Y2, a => Y);
    a_3 : VitalBuf (q => Y3, a => Y);
    a_4 : VitalBuf (q => Y4, a => Y);
    a_5 : VitalBuf (q => Y5, a => Y);
    a_6 : VitalBuf (q => Y6, a => Y);
    a_7 : VitalBuf (q => Y7, a => Y);
    a_8 : VitalBuf (q => Y8, a => Y);
    a_9 : VitalBuf (q => Y9, a => Y);
    a_10 : VitalBuf (q => Y10, a => Y);

    ----------------------------------------------------------------------------
        -- VITALBehavior Process
    ----------------------------------------------------------------------------
        VITALBehavior : PROCESS(A_ipd)

        -- Functionality Results Variables
        VARIABLE Y_zd        : std_ulogic := 'U';

        -- Output Glitch Detection Variables
        VARIABLE Y_GlitchData : VitalGlitchDataType;

    BEGIN

        ------------------------------------------------------------------------
        -- Functionality Section
        ------------------------------------------------------------------------
                Y_zd := VitalBUF(data=> A_ipd);

        ------------------------------------------------------------------------
        -- Path Delay Section
        ------------------------------------------------------------------------
        VitalPathDelay01 (
            OutSignal       =>  Y,
            OutSignalName   =>  "Y",
            OutTemp         =>  Y_zd,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Paths           => (
                0 => (InputChangeTime   => A_ipd'LAST_EVENT,
                      PathDelay         => tpd_A_Y1,
                      PathCondition     => TRUE ) ),
            GlitchData      => Y_GlitchData );

    END PROCESS;

END vhdl_behavioral;