dds.map.qmsg

dds实现波形的生成

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version " "Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jul 26 13:33:41 2006 " "Info: Processing started: Wed Jul 26 13:33:41 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off DDS -c DDS " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DDS -c DDS" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "REG10B.VHD 2 1 " "Info: Found 2 design units, including 1 entities, in source file REG10B.VHD" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 REG10B-behav " "Info: Found design unit 1: REG10B-behav" {  } { { "REG10B.VHD" "" { Text "D:/cwdds/REG10B.VHD" 8 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 REG10B " "Info: Found entity 1: REG10B" {  } { { "REG10B.VHD" "" { Text "D:/cwdds/REG10B.VHD" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "lpm_rom0.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file lpm_rom0.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lpm_rom0-SYN " "Info: Found design unit 1: lpm_rom0-SYN" {  } { { "lpm_rom0.vhd" "" { Text "D:/cwdds/lpm_rom0.vhd" 55 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 lpm_rom0 " "Info: Found entity 1: lpm_rom0" {  } { { "lpm_rom0.vhd" "" { Text "D:/cwdds/lpm_rom0.vhd" 45 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DDS_VHDL.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file DDS_VHDL.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 DDS_VHDL-one " "Info: Found design unit 1: DDS_VHDL-one" {  } { { "DDS_VHDL.vhd" "" { Text "D:/cwdds/DDS_VHDL.vhd" 10 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 DDS_VHDL " "Info: Found entity 1: DDS_VHDL" {  } { { "DDS_VHDL.vhd" "" { Text "D:/cwdds/DDS_VHDL.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ADDER10B.VHD 2 1 " "Info: Found 2 design units, including 1 entities, in source file ADDER10B.VHD" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ADDER10B-behav " "Info: Found design unit 1: ADDER10B-behav" {  } { { "ADDER10B.VHD" "" { Text "D:/cwdds/ADDER10B.VHD" 9 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 ADDER10B " "Info: Found entity 1: ADDER10B" {  } { { "ADDER10B.VHD" "" { Text "D:/cwdds/ADDER10B.VHD" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "DDS_VHDL " "Info: Elaborating entity \"DDS_VHDL\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ADDER10B ADDER10B:u1 " "Info: Elaborating entity \"ADDER10B\" for hierarchy \"ADDER10B:u1\"" {  } { { "DDS_VHDL.vhd" "u1" { Text "D:/cwdds/DDS_VHDL.vhd" 34 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "REG10B REG10B:u2 " "Info: Elaborating entity \"REG10B\" for hierarchy \"REG10B:u2\"" {  } { { "DDS_VHDL.vhd" "u2" { Text "D:/cwdds/DDS_VHDL.vhd" 36 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_rom0 lpm_rom0:u6 " "Info: Elaborating entity \"lpm_rom0\" for hierarchy \"lpm_rom0:u6\"" {  } { { "DDS_VHDL.vhd" "u6" { Text "D:/cwdds/DDS_VHDL.vhd" 38 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "e:/altera/quartus50/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file e:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "e:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 425 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram lpm_rom0:u6\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"lpm_rom0:u6\|altsyncram:altsyncram_component\"" {  } { { "lpm_rom0.vhd" "altsyncram_component" { Text "D:/cwdds/lpm_rom0.vhd" 86 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_obq.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_obq.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_obq " "Info: Found entity 1: altsyncram_obq" {  } { { "db/altsyncram_obq.tdf" "" { Text "D:/cwdds/db/altsyncram_obq.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_obq lpm_rom0:u6\|altsyncram:altsyncram_component\|altsyncram_obq:auto_generated " "Info: Elaborating entity \"altsyncram_obq\" for hierarchy \"lpm_rom0:u6\|altsyncram:altsyncram_component\|altsyncram_obq:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "e:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 903 3 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "51 " "Info: Implemented 51 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "11 " "Info: Implemented 11 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "10 " "Info: Implemented 10 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "20 " "Info: Implemented 20 logic cells" {  } {  } 0} { "Info" "ISCL_SCL_TM_RAMS" "10 " "Info: Implemented 10 RAM segments" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Jul 26 13:33:46 2006 " "Info: Processing ended: Wed Jul 26 13:33:46 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0}  } {  } 0}