dds_modelsim.xrf

dds实现波形的生成

vendor_name = ModelSim
source_file = 1, D:/cwdds/REG10B.VHD
source_file = 1, D:/cwdds/lpm_rom0.vhd
source_file = 1, D:/cwdds/DDS_VHDL.vhd
source_file = 1, D:/cwdds/ADDER10B.VHD
source_file = 1, e:/altera/quartus50/libraries/megafunctions/altsyncram.tdf
source_file = 1, e:/altera/quartus50/libraries/megafunctions/stratix_ram_block.inc
source_file = 1, e:/altera/quartus50/libraries/megafunctions/lpm_mux.inc
source_file = 1, e:/altera/quartus50/libraries/megafunctions/lpm_decode.inc
source_file = 1, e:/altera/quartus50/libraries/megafunctions/aglobal50.inc
source_file = 1, e:/altera/quartus50/libraries/megafunctions/altsyncram.inc
source_file = 1, e:/altera/quartus50/libraries/megafunctions/a_rdenreg.inc
source_file = 1, e:/altera/quartus50/libraries/megafunctions/altrom.inc
source_file = 1, e:/altera/quartus50/libraries/megafunctions/altram.inc
source_file = 1, e:/altera/quartus50/libraries/megafunctions/altdpram.inc
source_file = 1, e:/altera/quartus50/libraries/megafunctions/altqpram.inc
source_file = 1, e:/altera/quartus50/libraries/megafunctions/cbx.lst
source_file = 1, D:/cwdds/db/altsyncram_obq.tdf
source_file = 1, D:/cwdds/sinsin.mif
design_name = DDS_VHDL
instance = comp, CLK_aI, CLK, DDS_VHDL, 1
instance = comp, FWORD_a0_a_aI, FWORD[0], DDS_VHDL, 1
instance = comp, u2_aDOUT_a0_a_aI, u2|DOUT[0], DDS_VHDL, 1
instance = comp, u3_aDOUT_a0_a_aI, u3|DOUT[0], DDS_VHDL, 1
instance = comp, FWORD_a1_a_aI, FWORD[1], DDS_VHDL, 1
instance = comp, u2_aDOUT_a1_a_aI, u2|DOUT[1], DDS_VHDL, 1
instance = comp, u3_aDOUT_a1_a_aI, u3|DOUT[1], DDS_VHDL, 1
instance = comp, FWORD_a2_a_aI, FWORD[2], DDS_VHDL, 1
instance = comp, u2_aDOUT_a2_a_aI, u2|DOUT[2], DDS_VHDL, 1
instance = comp, u3_aDOUT_a2_a_aI, u3|DOUT[2], DDS_VHDL, 1
instance = comp, FWORD_a3_a_aI, FWORD[3], DDS_VHDL, 1
instance = comp, u2_aDOUT_a3_a_aI, u2|DOUT[3], DDS_VHDL, 1
instance = comp, u3_aDOUT_a3_a_aI, u3|DOUT[3], DDS_VHDL, 1
instance = comp, FWORD_a4_a_aI, FWORD[4], DDS_VHDL, 1
instance = comp, u2_aDOUT_a4_a_aI, u2|DOUT[4], DDS_VHDL, 1
instance = comp, u3_aDOUT_a4_a_aI, u3|DOUT[4], DDS_VHDL, 1
instance = comp, FWORD_a5_a_aI, FWORD[5], DDS_VHDL, 1
instance = comp, u2_aDOUT_a5_a_aI, u2|DOUT[5], DDS_VHDL, 1
instance = comp, u3_aDOUT_a5_a_aI, u3|DOUT[5], DDS_VHDL, 1
instance = comp, FWORD_a6_a_aI, FWORD[6], DDS_VHDL, 1
instance = comp, u2_aDOUT_a6_a_aI, u2|DOUT[6], DDS_VHDL, 1
instance = comp, u3_aDOUT_a6_a_aI, u3|DOUT[6], DDS_VHDL, 1
instance = comp, FWORD_a7_a_aI, FWORD[7], DDS_VHDL, 1
instance = comp, u2_aDOUT_a7_a_aI, u2|DOUT[7], DDS_VHDL, 1
instance = comp, u3_aDOUT_a7_a_aI, u3|DOUT[7], DDS_VHDL, 1
instance = comp, FWORD_a8_a_aI, FWORD[8], DDS_VHDL, 1
instance = comp, u2_aDOUT_a8_a_aI, u2|DOUT[8], DDS_VHDL, 1
instance = comp, u3_aDOUT_a8_a_aI, u3|DOUT[8], DDS_VHDL, 1
instance = comp, FWORD_a9_a_aI, FWORD[9], DDS_VHDL, 1
instance = comp, u2_aDOUT_a9_a_aI, u2|DOUT[9], DDS_VHDL, 1
instance = comp, u3_aDOUT_a9_a_aI, u3|DOUT[9], DDS_VHDL, 1
instance = comp, u6_aaltsyncram_component_aauto_generated_aram_block1a0, u6|altsyncram_component|auto_generated|ram_block1a0, DDS_VHDL, 1
instance = comp, u6_aaltsyncram_component_aauto_generated_aram_block1a1, u6|altsyncram_component|auto_generated|ram_block1a1, DDS_VHDL, 1
instance = comp, u6_aaltsyncram_component_aauto_generated_aram_block1a3, u6|altsyncram_component|auto_generated|ram_block1a3, DDS_VHDL, 1
instance = comp, FOUT_a0_a_aI, FOUT[0], DDS_VHDL, 1
instance = comp, FOUT_a1_a_aI, FOUT[1], DDS_VHDL, 1
instance = comp, FOUT_a2_a_aI, FOUT[2], DDS_VHDL, 1
instance = comp, FOUT_a3_a_aI, FOUT[3], DDS_VHDL, 1
instance = comp, FOUT_a4_a_aI, FOUT[4], DDS_VHDL, 1
instance = comp, FOUT_a5_a_aI, FOUT[5], DDS_VHDL, 1
instance = comp, FOUT_a6_a_aI, FOUT[6], DDS_VHDL, 1
instance = comp, FOUT_a7_a_aI, FOUT[7], DDS_VHDL, 1
instance = comp, FOUT_a8_a_aI, FOUT[8], DDS_VHDL, 1
instance = comp, FOUT_a9_a_aI, FOUT[9], DDS_VHDL, 1