dds.fit.qmsg

dds实现波形的生成

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version " "Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jul 26 13:33:47 2006 " "Info: Processing started: Wed Jul 26 13:33:47 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off DDS -c DDS " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off DDS -c DDS" {  } {  } 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "DDS EP1SGX40GF1020C5 " "Info: Selected device EP1SGX40GF1020C5 for design \"DDS\"" {  } {  } 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices. " { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1SGX25DF1020C5 " "Info: Device EP1SGX25DF1020C5 is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1SGX25FF1020C5 " "Info: Device EP1SGX25FF1020C5 is compatible" {  } {  } 2} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1SGX40DF1020C5 " "Info: Device EP1SGX40DF1020C5 is compatible" {  } {  } 2}  } {  } 2}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "21 21 " "Info: No exact pin location assignment(s) for 21 pins of 21 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "FOUT\[0\] " "Info: Pin FOUT\[0\] not assigned to an exact location on the device" {  } { { "DDS_VHDL.vhd" "" { Text "D:/cwdds/DDS_VHDL.vhd" 7 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FOUT\[0\]" } } } } { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "" { FOUT[0] } "NODE_NAME" } "" } } { "D:/cwdds/DDS.fld" "" { Floorplan "D:/cwdds/DDS.fld" "" "" { FOUT[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "FOUT\[1\] " "Info: Pin FOUT\[1\] not assigned to an exact location on the device" {  } { { "DDS_VHDL.vhd" "" { Text "D:/cwdds/DDS_VHDL.vhd" 7 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FOUT\[1\]" } } } } { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "" { FOUT[1] } "NODE_NAME" } "" } } { "D:/cwdds/DDS.fld" "" { Floorplan "D:/cwdds/DDS.fld" "" "" { FOUT[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "FOUT\[2\] " "Info: Pin FOUT\[2\] not assigned to an exact location on the device" {  } { { "DDS_VHDL.vhd" "" { Text "D:/cwdds/DDS_VHDL.vhd" 7 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FOUT\[2\]" } } } } { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "" { FOUT[2] } "NODE_NAME" } "" } } { "D:/cwdds/DDS.fld" "" { Floorplan "D:/cwdds/DDS.fld" "" "" { FOUT[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "FOUT\[3\] " "Info: Pin FOUT\[3\] not assigned to an exact location on the device" {  } { { "DDS_VHDL.vhd" "" { Text "D:/cwdds/DDS_VHDL.vhd" 7 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FOUT\[3\]" } } } } { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "" { FOUT[3] } "NODE_NAME" } "" } } { "D:/cwdds/DDS.fld" "" { Floorplan "D:/cwdds/DDS.fld" "" "" { FOUT[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "FOUT\[4\] " "Info: Pin FOUT\[4\] not assigned to an exact location on the device" {  } { { "DDS_VHDL.vhd" "" { Text "D:/cwdds/DDS_VHDL.vhd" 7 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FOUT\[4\]" } } } } { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "" { FOUT[4] } "NODE_NAME" } "" } } { "D:/cwdds/DDS.fld" "" { Floorplan "D:/cwdds/DDS.fld" "" "" { FOUT[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "FOUT\[5\] " "Info: Pin FOUT\[5\] not assigned to an exact location on the device" {  } { { "DDS_VHDL.vhd" "" { Text "D:/cwdds/DDS_VHDL.vhd" 7 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FOUT\[5\]" } } } } { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "" { FOUT[5] } "NODE_NAME" } "" } } { "D:/cwdds/DDS.fld" "" { Floorplan "D:/cwdds/DDS.fld" "" "" { FOUT[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "FOUT\[6\] " "Info: Pin FOUT\[6\] not assigned to an exact location on the device" {  } { { "DDS_VHDL.vhd" "" { Text "D:/cwdds/DDS_VHDL.vhd" 7 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FOUT\[6\]" } } } } { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "" { FOUT[6] } "NODE_NAME" } "" } } { "D:/cwdds/DDS.fld" "" { Floorplan "D:/cwdds/DDS.fld" "" "" { FOUT[6] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "FOUT\[7\] " "Info: Pin FOUT\[7\] not assigned to an exact location on the device" {  } { { "DDS_VHDL.vhd" "" { Text "D:/cwdds/DDS_VHDL.vhd" 7 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FOUT\[7\]" } } } } { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "" { FOUT[7] } "NODE_NAME" } "" } } { "D:/cwdds/DDS.fld" "" { Floorplan "D:/cwdds/DDS.fld" "" "" { FOUT[7] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "FOUT\[8\] " "Info: Pin FOUT\[8\] not assigned to an exact location on the device" {  } { { "DDS_VHDL.vhd" "" { Text "D:/cwdds/DDS_VHDL.vhd" 7 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FOUT\[8\]" } } } } { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "" { FOUT[8] } "NODE_NAME" } "" } } { "D:/cwdds/DDS.fld" "" { Floorplan "D:/cwdds/DDS.fld" "" "" { FOUT[8] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "FOUT\[9\] " "Info: Pin FOUT\[9\] not assigned to an exact location on the device" {  } { { "DDS_VHDL.vhd" "" { Text "D:/cwdds/DDS_VHDL.vhd" 7 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FOUT\[9\]" } } } } { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "" { FOUT[9] } "NODE_NAME" } "" } } { "D:/cwdds/DDS.fld" "" { Floorplan "D:/cwdds/DDS.fld" "" "" { FOUT[9] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "CLK " "Info: Pin CLK not assigned to an exact location on the device" {  } { { "DDS_VHDL.vhd" "" { Text "D:/cwdds/DDS_VHDL.vhd" 5 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } } { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "" { CLK } "NODE_NAME" } "" } } { "D:/cwdds/DDS.fld" "" { Floorplan "D:/cwdds/DDS.fld" "" "" { CLK } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "FWORD\[0\] " "Info: Pin FWORD\[0\] not assigned to an exact location on the device" {  } { { "DDS_VHDL.vhd" "" { Text "D:/cwdds/DDS_VHDL.vhd" 6 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FWORD\[0\]" } } } } { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "" { FWORD[0] } "NODE_NAME" } "" } } { "D:/cwdds/DDS.fld" "" { Floorplan "D:/cwdds/DDS.fld" "" "" { FWORD[0] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "FWORD\[1\] " "Info: Pin FWORD\[1\] not assigned to an exact location on the device" {  } { { "DDS_VHDL.vhd" "" { Text "D:/cwdds/DDS_VHDL.vhd" 6 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FWORD\[1\]" } } } } { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "" { FWORD[1] } "NODE_NAME" } "" } } { "D:/cwdds/DDS.fld" "" { Floorplan "D:/cwdds/DDS.fld" "" "" { FWORD[1] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "FWORD\[2\] " "Info: Pin FWORD\[2\] not assigned to an exact location on the device" {  } { { "DDS_VHDL.vhd" "" { Text "D:/cwdds/DDS_VHDL.vhd" 6 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FWORD\[2\]" } } } } { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "" { FWORD[2] } "NODE_NAME" } "" } } { "D:/cwdds/DDS.fld" "" { Floorplan "D:/cwdds/DDS.fld" "" "" { FWORD[2] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "FWORD\[3\] " "Info: Pin FWORD\[3\] not assigned to an exact location on the device" {  } { { "DDS_VHDL.vhd" "" { Text "D:/cwdds/DDS_VHDL.vhd" 6 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FWORD\[3\]" } } } } { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "" { FWORD[3] } "NODE_NAME" } "" } } { "D:/cwdds/DDS.fld" "" { Floorplan "D:/cwdds/DDS.fld" "" "" { FWORD[3] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "FWORD\[4\] " "Info: Pin FWORD\[4\] not assigned to an exact location on the device" {  } { { "DDS_VHDL.vhd" "" { Text "D:/cwdds/DDS_VHDL.vhd" 6 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FWORD\[4\]" } } } } { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "" { FWORD[4] } "NODE_NAME" } "" } } { "D:/cwdds/DDS.fld" "" { Floorplan "D:/cwdds/DDS.fld" "" "" { FWORD[4] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "FWORD\[5\] " "Info: Pin FWORD\[5\] not assigned to an exact location on the device" {  } { { "DDS_VHDL.vhd" "" { Text "D:/cwdds/DDS_VHDL.vhd" 6 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FWORD\[5\]" } } } } { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "" { FWORD[5] } "NODE_NAME" } "" } } { "D:/cwdds/DDS.fld" "" { Floorplan "D:/cwdds/DDS.fld" "" "" { FWORD[5] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "FWORD\[6\] " "Info: Pin FWORD\[6\] not assigned to an exact location on the device" {  } { { "DDS_VHDL.vhd" "" { Text "D:/cwdds/DDS_VHDL.vhd" 6 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FWORD\[6\]" } } } } { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "" { FWORD[6] } "NODE_NAME" } "" } } { "D:/cwdds/DDS.fld" "" { Floorplan "D:/cwdds/DDS.fld" "" "" { FWORD[6] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "FWORD\[7\] " "Info: Pin FWORD\[7\] not assigned to an exact location on the device" {  } { { "DDS_VHDL.vhd" "" { Text "D:/cwdds/DDS_VHDL.vhd" 6 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FWORD\[7\]" } } } } { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "" { FWORD[7] } "NODE_NAME" } "" } } { "D:/cwdds/DDS.fld" "" { Floorplan "D:/cwdds/DDS.fld" "" "" { FWORD[7] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "FWORD\[8\] " "Info: Pin FWORD\[8\] not assigned to an exact location on the device" {  } { { "DDS_VHDL.vhd" "" { Text "D:/cwdds/DDS_VHDL.vhd" 6 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FWORD\[8\]" } } } } { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "" { FWORD[8] } "NODE_NAME" } "" } } { "D:/cwdds/DDS.fld" "" { Floorplan "D:/cwdds/DDS.fld" "" "" { FWORD[8] } "NODE_NAME" } }  } 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "FWORD\[9\] " "Info: Pin FWORD\[9\] not assigned to an exact location on the device" {  } { { "DDS_VHDL.vhd" "" { Text "D:/cwdds/DDS_VHDL.vhd" 6 -1 0 } } { "e:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "e:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "FWORD\[9\]" } } } } { "D:/cwdds/db/DDS_cmp.qrpt" "" { Report "D:/cwdds/db/DDS_cmp.qrpt" Compiler "DDS" "UNKNOWN" "V1" "D:/cwdds/db/DDS.quartus_db" { Floorplan "D:/cwdds/" "" "" { FWORD[9] } "NODE_NAME" } "" } } { "D:/cwdds/DDS.fld" "" { Floorplan "D:/cwdds/DDS.fld" "" "" { FWORD[9] } "NODE_NAME" } }  } 0}  } {  } 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "CLK Global clock in PIN D16 " "Info: Automatically promoted signal \"CLK\" to use Global clock in PIN D16" {  } { { "DDS_VHDL.vhd" "" { Text "D:/cwdds/DDS_VHDL.vhd" 5 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Info: Start inferring scan chains for DSP blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Info: Inferring scan chains for DSP blocks is complete" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_MAC_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, RAM blocks, and DSP blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_MAC_RAM_PACKING" "" "Info: Finished moving registers into LUTs, I/O cells, DSP blocks, and RAM blocks" {  } {  } 0}