代码搜索:VHDL
找到约 10,000 项符合「VHDL」的源代码
代码结果 10,000
www.eeworm.com/read/291438/8420371
qmsg traffic.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info:
www.eeworm.com/read/290091/8506123
qmsg prev_cmp_int2bit.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
www.eeworm.com/read/290091/8506126
qmsg int2bit.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
www.eeworm.com/read/288669/8614690
qmsg dzxs.fit.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartu
www.eeworm.com/read/387424/8683941
txt run_options.txt
#-- Synplicity, Inc.
#-- Version 9.0
#-- Project file C:\projects\REFDES~1\mico8\MICO8_~3\BLOCK_~1\run_options.txt
#-- Written on Fri Mar 14 11:39:52 2008
#add_file options
add_file -vhdl -li
www.eeworm.com/read/387416/8685284
log coregen.log
# Xilinx CORE Generator 6.1i
# User = 刘韬
Initializing default project...
Loading plug-ins...
All runtime messages will be recorded in E:\刘韬\MY_WORK\FPGA\程序\I2C\coregen.log
# busformat=BusFormatAn
www.eeworm.com/read/426991/8987713
qmsg ram.fit.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
www.eeworm.com/read/426986/8987970
qmsg module.tan.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
www.eeworm.com/read/283738/8991675
npl myfpga.npl
JDF G
// Created by Project Navigator ver 1.0
PROJECT MyFPGA
DESIGN myfpga
DEVFAM spartan2
DEVFAMTIME 0
DEVICE xc2s15
DEVICETIME 0
DEVPKG cs144
DEVPKGTIME 0
DEVSPEED -6
DEVSPEEDTIME 0
DEVT
www.eeworm.com/read/185226/9049417
cfg compxlib.cfg
#*****************************************************************
# compxlib initialization file (compxlib.cfg) *
#