prev_cmp_int2bit.map.qmsg

整型数据转换为二进制数据的实验。全部都是整个文件夹上传的。可以用QUARTUS2直接运行的。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Web Edition " "Info: Version 7.1 Build 156 04/30/2007 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Dec 08 21:36:00 2007 " "Info: Processing started: Sat Dec 08 21:36:00 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off int2bit -c int2bit " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off int2bit -c int2bit" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Error" "EVRFX_VHDL_SYNTAX_ERROR" "\"IF\";  expecting \"end\", or \"(\", or an identifier (\"if\" is a reserved keyword), or a concurrent statement int2bit.vhd(13) " "Error (10500): VHDL syntax error at int2bit.vhd(13) near text \"IF\";  expecting \"end\", or \"(\", or an identifier (\"if\" is a reserved keyword), or a concurrent statement" {  } { { "int2bit.vhd" "" { Text "F:/school/EDA/王志娟EDA/int2bit/int2bit.vhd" 13 0 0 } }  } 0 10500 "VHDL syntax error at %2!s! near text %1!s!" 0 0 "" 0}
{ "Error" "EVRFX_VHDL_SYNTAX_ERROR" "\"tmp_intnum\";  expecting \"<=\" int2bit.vhd(14) " "Error (10500): VHDL syntax error at int2bit.vhd(14) near text \"tmp_intnum\";  expecting \"<=\"" {  } { { "int2bit.vhd" "" { Text "F:/school/EDA/王志娟EDA/int2bit/int2bit.vhd" 14 0 0 } }  } 0 10500 "VHDL syntax error at %2!s! near text %1!s!" 0 0 "" 0}
{ "Error" "EVRFX_VHDL_SYNTAX_ERROR" "\"IF\";  expecting \";\", or an identifier (\"if\" is a reserved keyword), or \"architecture\" int2bit.vhd(16) " "Error (10500): VHDL syntax error at int2bit.vhd(16) near text \"IF\";  expecting \";\", or an identifier (\"if\" is a reserved keyword), or \"architecture\"" {  } { { "int2bit.vhd" "" { Text "F:/school/EDA/王志娟EDA/int2bit/int2bit.vhd" 16 0 0 } }  } 0 10500 "VHDL syntax error at %2!s! near text %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "int2bit.vhd 0 0 " "Info: Found 0 design units, including 0 entities, in source file int2bit.vhd" {  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 3 s 0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 3 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "144 " "Info: Allocated 144 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Error" "EQEXE_END_BANNER_TIME" "Sat Dec 08 21:36:03 2007 " "Error: Processing ended: Sat Dec 08 21:36:03 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:03 " "Error: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}