traffic.map.qmsg

一个简单的交通灯程序(包括验证,主程序,和译码程序),在ALTER DE2板上实现

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Apr 03 13:51:44 2007 " "Info: Processing started: Tue Apr 03 13:51:44 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off traffic -c traffic " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off traffic -c traffic" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "traffic.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file traffic.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 traffic-arch " "Info: Found design unit 1: traffic-arch" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 14 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 traffic " "Info: Found entity 1: traffic" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "All traffic.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file All traffic.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 All traffic " "Info: Found entity 1: All traffic" {  } { { "All traffic.bdf" "" { Schematic "E:/FPGA/EDA4.3/traffic/All traffic.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DECL7S.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file DECL7S.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 DECL7S-ONE " "Info: Found design unit 1: DECL7S-ONE" {  } { { "DECL7S.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/DECL7S.vhd" 7 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 DECL7S " "Info: Found entity 1: DECL7S" {  } { { "DECL7S.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/DECL7S.vhd" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "traffic " "Info: Elaborating entity \"traffic\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "east_west traffic.vhd(48) " "Warning: VHDL Process Statement warning at traffic.vhd(48): signal \"east_west\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 48 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "east_west traffic.vhd(49) " "Warning: VHDL Process Statement warning at traffic.vhd(49): signal \"east_west\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 49 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "south_north traffic.vhd(50) " "Warning: VHDL Process Statement warning at traffic.vhd(50): signal \"south_north\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 50 0 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "south_north traffic.vhd(51) " "Warning: VHDL Process Statement warning at traffic.vhd(51): signal \"south_north\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 51 0 0 } }  } 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 8 -1 0 } } { "traffic.vhd" "" { Text "E:/FPGA/EDA4.3/traffic/traffic.vhd" 8 -1 0 } }  } 0}
{ "Info" "IOPT_MLS_DEV_CLRN_SETS_REGISTERS" "" "Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "119 " "Info: Implemented 119 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "38 " "Info: Implemented 38 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "79 " "Info: Implemented 79 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 03 13:51:46 2007 " "Info: Processing ended: Tue Apr 03 13:51:46 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}