ram.fit.qmsg

RAM存储器的源程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue May 13 17:46:37 2008 " "Info: Processing started: Tue May 13 17:46:37 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off ram -c ram " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off ram -c ram" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "ram EP1C12Q240C8 " "Info: Selected device EP1C12Q240C8 for design \"ram\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C6Q240C8 " "Info: Device EP1C6Q240C8 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "24 24 " "Info: No exact pin location assignment(s) for 24 pins of 24 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "dataout\[0\] " "Info: Pin dataout\[0\] not assigned to an exact location on the device" {  } { { "ram.vhd" "" { Text "E:/vhdl code/ram/ram.vhd" 13 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "dataout\[0\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ram" "UNKNOWN" "V1" "E:/vhdl code/ram/db/ram.quartus_db" { Floorplan "E:/vhdl code/ram/" "" "" { dataout[0] } "NODE_NAME" } "" } } { "E:/vhdl code/ram/ram.fld" "" { Floorplan "E:/vhdl code/ram/ram.fld" "" "" { dataout[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "dataout\[1\] " "Info: Pin dataout\[1\] not assigned to an exact location on the device" {  } { { "ram.vhd" "" { Text "E:/vhdl code/ram/ram.vhd" 13 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "dataout\[1\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ram" "UNKNOWN" "V1" "E:/vhdl code/ram/db/ram.quartus_db" { Floorplan "E:/vhdl code/ram/" "" "" { dataout[1] } "NODE_NAME" } "" } } { "E:/vhdl code/ram/ram.fld" "" { Floorplan "E:/vhdl code/ram/ram.fld" "" "" { dataout[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "dataout\[2\] " "Info: Pin dataout\[2\] not assigned to an exact location on the device" {  } { { "ram.vhd" "" { Text "E:/vhdl code/ram/ram.vhd" 13 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "dataout\[2\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ram" "UNKNOWN" "V1" "E:/vhdl code/ram/db/ram.quartus_db" { Floorplan "E:/vhdl code/ram/" "" "" { dataout[2] } "NODE_NAME" } "" } } { "E:/vhdl code/ram/ram.fld" "" { Floorplan "E:/vhdl code/ram/ram.fld" "" "" { dataout[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "dataout\[3\] " "Info: Pin dataout\[3\] not assigned to an exact location on the device" {  } { { "ram.vhd" "" { Text "E:/vhdl code/ram/ram.vhd" 13 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "dataout\[3\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ram" "UNKNOWN" "V1" "E:/vhdl code/ram/db/ram.quartus_db" { Floorplan "E:/vhdl code/ram/" "" "" { dataout[3] } "NODE_NAME" } "" } } { "E:/vhdl code/ram/ram.fld" "" { Floorplan "E:/vhdl code/ram/ram.fld" "" "" { dataout[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "dataout\[4\] " "Info: Pin dataout\[4\] not assigned to an exact location on the device" {  } { { "ram.vhd" "" { Text "E:/vhdl code/ram/ram.vhd" 13 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "dataout\[4\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ram" "UNKNOWN" "V1" "E:/vhdl code/ram/db/ram.quartus_db" { Floorplan "E:/vhdl code/ram/" "" "" { dataout[4] } "NODE_NAME" } "" } } { "E:/vhdl code/ram/ram.fld" "" { Floorplan "E:/vhdl code/ram/ram.fld" "" "" { dataout[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "dataout\[5\] " "Info: Pin dataout\[5\] not assigned to an exact location on the device" {  } { { "ram.vhd" "" { Text "E:/vhdl code/ram/ram.vhd" 13 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "dataout\[5\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ram" "UNKNOWN" "V1" "E:/vhdl code/ram/db/ram.quartus_db" { Floorplan "E:/vhdl code/ram/" "" "" { dataout[5] } "NODE_NAME" } "" } } { "E:/vhdl code/ram/ram.fld" "" { Floorplan "E:/vhdl code/ram/ram.fld" "" "" { dataout[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "dataout\[6\] " "Info: Pin dataout\[6\] not assigned to an exact location on the device" {  } { { "ram.vhd" "" { Text "E:/vhdl code/ram/ram.vhd" 13 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "dataout\[6\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ram" "UNKNOWN" "V1" "E:/vhdl code/ram/db/ram.quartus_db" { Floorplan "E:/vhdl code/ram/" "" "" { dataout[6] } "NODE_NAME" } "" } } { "E:/vhdl code/ram/ram.fld" "" { Floorplan "E:/vhdl code/ram/ram.fld" "" "" { dataout[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "dataout\[7\] " "Info: Pin dataout\[7\] not assigned to an exact location on the device" {  } { { "ram.vhd" "" { Text "E:/vhdl code/ram/ram.vhd" 13 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "dataout\[7\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ram" "UNKNOWN" "V1" "E:/vhdl code/ram/db/ram.quartus_db" { Floorplan "E:/vhdl code/ram/" "" "" { dataout[7] } "NODE_NAME" } "" } } { "E:/vhdl code/ram/ram.fld" "" { Floorplan "E:/vhdl code/ram/ram.fld" "" "" { dataout[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "addr\[2\] " "Info: Pin addr\[2\] not assigned to an exact location on the device" {  } { { "ram.vhd" "" { Text "E:/vhdl code/ram/ram.vhd" 8 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "addr\[2\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ram" "UNKNOWN" "V1" "E:/vhdl code/ram/db/ram.quartus_db" { Floorplan "E:/vhdl code/ram/" "" "" { addr[2] } "NODE_NAME" } "" } } { "E:/vhdl code/ram/ram.fld" "" { Floorplan "E:/vhdl code/ram/ram.fld" "" "" { addr[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "addr\[3\] " "Info: Pin addr\[3\] not assigned to an exact location on the device" {  } { { "ram.vhd" "" { Text "E:/vhdl code/ram/ram.vhd" 8 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "addr\[3\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ram" "UNKNOWN" "V1" "E:/vhdl code/ram/db/ram.quartus_db" { Floorplan "E:/vhdl code/ram/" "" "" { addr[3] } "NODE_NAME" } "" } } { "E:/vhdl code/ram/ram.fld" "" { Floorplan "E:/vhdl code/ram/ram.fld" "" "" { addr[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "addr\[1\] " "Info: Pin addr\[1\] not assigned to an exact location on the device" {  } { { "ram.vhd" "" { Text "E:/vhdl code/ram/ram.vhd" 8 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "addr\[1\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ram" "UNKNOWN" "V1" "E:/vhdl code/ram/db/ram.quartus_db" { Floorplan "E:/vhdl code/ram/" "" "" { addr[1] } "NODE_NAME" } "" } } { "E:/vhdl code/ram/ram.fld" "" { Floorplan "E:/vhdl code/ram/ram.fld" "" "" { addr[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "addr\[0\] " "Info: Pin addr\[0\] not assigned to an exact location on the device" {  } { { "ram.vhd" "" { Text "E:/vhdl code/ram/ram.vhd" 8 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "addr\[0\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ram" "UNKNOWN" "V1" "E:/vhdl code/ram/db/ram.quartus_db" { Floorplan "E:/vhdl code/ram/" "" "" { addr[0] } "NODE_NAME" } "" } } { "E:/vhdl code/ram/ram.fld" "" { Floorplan "E:/vhdl code/ram/ram.fld" "" "" { addr[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "addr\[4\] " "Info: Pin addr\[4\] not assigned to an exact location on the device" {  } { { "ram.vhd" "" { Text "E:/vhdl code/ram/ram.vhd" 8 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "addr\[4\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ram" "UNKNOWN" "V1" "E:/vhdl code/ram/db/ram.quartus_db" { Floorplan "E:/vhdl code/ram/" "" "" { addr[4] } "NODE_NAME" } "" } } { "E:/vhdl code/ram/ram.fld" "" { Floorplan "E:/vhdl code/ram/ram.fld" "" "" { addr[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "rd " "Info: Pin rd not assigned to an exact location on the device" {  } { { "ram.vhd" "" { Text "E:/vhdl code/ram/ram.vhd" 10 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "rd" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ram" "UNKNOWN" "V1" "E:/vhdl code/ram/db/ram.quartus_db" { Floorplan "E:/vhdl code/ram/" "" "" { rd } "NODE_NAME" } "" } } { "E:/vhdl code/ram/ram.fld" "" { Floorplan "E:/vhdl code/ram/ram.fld" "" "" { rd } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "cs " "Info: Pin cs not assigned to an exact location on the device" {  } { { "ram.vhd" "" { Text "E:/vhdl code/ram/ram.vhd" 11 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "cs" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ram" "UNKNOWN" "V1" "E:/vhdl code/ram/db/ram.quartus_db" { Floorplan "E:/vhdl code/ram/" "" "" { cs } "NODE_NAME" } "" } } { "E:/vhdl code/ram/ram.fld" "" { Floorplan "E:/vhdl code/ram/ram.fld" "" "" { cs } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "datain\[0\] " "Info: Pin datain\[0\] not assigned to an exact location on the device" {  } { { "ram.vhd" "" { Text "E:/vhdl code/ram/ram.vhd" 12 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "datain\[0\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ram" "UNKNOWN" "V1" "E:/vhdl code/ram/db/ram.quartus_db" { Floorplan "E:/vhdl code/ram/" "" "" { datain[0] } "NODE_NAME" } "" } } { "E:/vhdl code/ram/ram.fld" "" { Floorplan "E:/vhdl code/ram/ram.fld" "" "" { datain[0] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "wr " "Info: Pin wr not assigned to an exact location on the device" {  } { { "ram.vhd" "" { Text "E:/vhdl code/ram/ram.vhd" 9 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "wr" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ram" "UNKNOWN" "V1" "E:/vhdl code/ram/db/ram.quartus_db" { Floorplan "E:/vhdl code/ram/" "" "" { wr } "NODE_NAME" } "" } } { "E:/vhdl code/ram/ram.fld" "" { Floorplan "E:/vhdl code/ram/ram.fld" "" "" { wr } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "datain\[1\] " "Info: Pin datain\[1\] not assigned to an exact location on the device" {  } { { "ram.vhd" "" { Text "E:/vhdl code/ram/ram.vhd" 12 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "datain\[1\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ram" "UNKNOWN" "V1" "E:/vhdl code/ram/db/ram.quartus_db" { Floorplan "E:/vhdl code/ram/" "" "" { datain[1] } "NODE_NAME" } "" } } { "E:/vhdl code/ram/ram.fld" "" { Floorplan "E:/vhdl code/ram/ram.fld" "" "" { datain[1] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "datain\[2\] " "Info: Pin datain\[2\] not assigned to an exact location on the device" {  } { { "ram.vhd" "" { Text "E:/vhdl code/ram/ram.vhd" 12 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "datain\[2\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ram" "UNKNOWN" "V1" "E:/vhdl code/ram/db/ram.quartus_db" { Floorplan "E:/vhdl code/ram/" "" "" { datain[2] } "NODE_NAME" } "" } } { "E:/vhdl code/ram/ram.fld" "" { Floorplan "E:/vhdl code/ram/ram.fld" "" "" { datain[2] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "datain\[3\] " "Info: Pin datain\[3\] not assigned to an exact location on the device" {  } { { "ram.vhd" "" { Text "E:/vhdl code/ram/ram.vhd" 12 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "datain\[3\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ram" "UNKNOWN" "V1" "E:/vhdl code/ram/db/ram.quartus_db" { Floorplan "E:/vhdl code/ram/" "" "" { datain[3] } "NODE_NAME" } "" } } { "E:/vhdl code/ram/ram.fld" "" { Floorplan "E:/vhdl code/ram/ram.fld" "" "" { datain[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "datain\[4\] " "Info: Pin datain\[4\] not assigned to an exact location on the device" {  } { { "ram.vhd" "" { Text "E:/vhdl code/ram/ram.vhd" 12 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "datain\[4\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ram" "UNKNOWN" "V1" "E:/vhdl code/ram/db/ram.quartus_db" { Floorplan "E:/vhdl code/ram/" "" "" { datain[4] } "NODE_NAME" } "" } } { "E:/vhdl code/ram/ram.fld" "" { Floorplan "E:/vhdl code/ram/ram.fld" "" "" { datain[4] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "datain\[5\] " "Info: Pin datain\[5\] not assigned to an exact location on the device" {  } { { "ram.vhd" "" { Text "E:/vhdl code/ram/ram.vhd" 12 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "datain\[5\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ram" "UNKNOWN" "V1" "E:/vhdl code/ram/db/ram.quartus_db" { Floorplan "E:/vhdl code/ram/" "" "" { datain[5] } "NODE_NAME" } "" } } { "E:/vhdl code/ram/ram.fld" "" { Floorplan "E:/vhdl code/ram/ram.fld" "" "" { datain[5] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "datain\[6\] " "Info: Pin datain\[6\] not assigned to an exact location on the device" {  } { { "ram.vhd" "" { Text "E:/vhdl code/ram/ram.vhd" 12 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "datain\[6\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ram" "UNKNOWN" "V1" "E:/vhdl code/ram/db/ram.quartus_db" { Floorplan "E:/vhdl code/ram/" "" "" { datain[6] } "NODE_NAME" } "" } } { "E:/vhdl code/ram/ram.fld" "" { Floorplan "E:/vhdl code/ram/ram.fld" "" "" { datain[6] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "datain\[7\] " "Info: Pin datain\[7\] not assigned to an exact location on the device" {  } { { "ram.vhd" "" { Text "E:/vhdl code/ram/ram.vhd" 12 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "datain\[7\]" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ram" "UNKNOWN" "V1" "E:/vhdl code/ram/db/ram.quartus_db" { Floorplan "E:/vhdl code/ram/" "" "" { datain[7] } "NODE_NAME" } "" } } { "E:/vhdl code/ram/ram.fld" "" { Floorplan "E:/vhdl code/ram/ram.fld" "" "" { datain[7] } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0}  } {  } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0}  } {  } 0 0 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Performing register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Completed register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources" {  } {  } 0 0 "DQS I/O pins require %1!d! global routing resources" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "rtl~0 Global clock " "Info: Automatically promoted signal \"rtl~0\" to use Global clock" {  } { { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "rtl~0" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ram" "UNKNOWN" "V1" "E:/vhdl code/ram/db/ram.quartus_db" { Floorplan "E:/vhdl code/ram/" "" "" { rtl~0 } "NODE_NAME" } "" } } { "E:/vhdl code/ram/ram.fld" "" { Floorplan "E:/vhdl code/ram/ram.fld" "" "" { rtl~0 } "NODE_NAME" } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "rtl~1 Global clock " "Info: Automatically promoted signal \"rtl~1\" to use Global clock" {  } { { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "rtl~1" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ram" "UNKNOWN" "V1" "E:/vhdl code/ram/db/ram.quartus_db" { Floorplan "E:/vhdl code/ram/" "" "" { rtl~1 } "NODE_NAME" } "" } } { "E:/vhdl code/ram/ram.fld" "" { Floorplan "E:/vhdl code/ram/ram.fld" "" "" { rtl~1 } "NODE_NAME" } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "rtl~10 Global clock " "Info: Automatically promoted signal \"rtl~10\" to use Global clock" {  } { { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "rtl~10" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "ram" "UNKNOWN" "V1" "E:/vhdl code/ram/db/ram.quartus_db" { Floorplan "E:/vhdl code/ram/" "" "" { rtl~10 } "NODE_NAME" } "" } } { "E:/vhdl code/ram/ram.fld" "" { Floorplan "E:/vhdl code/ram/ram.fld" "" "" { rtl~10 } "NODE_NAME" } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}