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base-t0-vhdl-dsp.txt

FSK调制与解调VHDL程序及仿真 1. FSK调制VHDL程序 --文件名：PL_FSK --功能：基于VHDL硬件描述语言，对基带信号进行FSK调制 --最后修改日期：2004.3.16 library ieee; use ieee.std_logic_arith.all; use ieee.std_logic_1164.all;

vhdl.syn

; TextPad keyword syntax file for VHDL ; Contributed by Derek Roberts C=1 [Syntax] Namespace1 = 6 IgnoreCase = Yes InitKeyWordChars = A-Za-z_` KeyWordChars = A-Za-z0-9_ PreprocStart = # S

xhdl_std_logic.vhdl

-- -- Copyright Notice and Proprietary Information -- -- Copyright (C) 1997-2000 X-Tek Corporation. All rights reserved. This Software -- and documentation are owned by X-Tek Corporation, and may be

xhdl_misc.vhdl

-- -- Copyright Notice and Proprietary Information -- -- Copyright (C) 1997-2000 X-Tek Corporation. All rights reserved. This Software -- and documentation are owned by X-Tek Corporation, and may be

xhdl_bit.vhdl

-- -- Copyright Notice and Proprietary Information -- -- Copyright (C) 1997-2000 X-Tek Corporation. All rights reserved. This Software -- and documentation are owned by X-Tek Corporation, and may be

xhdl_std_ulogic.vhdl

-- -- Copyright Notice and Proprietary Information -- -- Copyright (C) 1997-2000 X-Tek Corporation. All rights reserved. This Software -- and documentation are owned by X-Tek Corporation, and may be

xhdl_std_logic.vhdl

-- -- Copyright Notice and Proprietary Information -- -- Copyright (C) 1997-2002 X-Tek Corporation. All rights reserved. This Software -- and documentation are owned by X-Tek Corporation, and may be

xhdl_bit.vhdl

-- -- Copyright Notice and Proprietary Information -- -- Copyright (C) 1997-2002 X-Tek Corporation. All rights reserved. This Software -- and documentation are owned by X-Tek Corporation, and may be

xhdl_std_ulogic.vhdl

-- -- Copyright Notice and Proprietary Information -- -- Copyright (C) 1997-2002 X-Tek Corporation. All rights reserved. This Software -- and documentation are owned by X-Tek Corporation, and may be

main.vhdl

Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all; Entity topclock is Port(clk,reset:in std_logic; --S1,m1,h1:in std_logic_vector(7 downto