alu.vhdl

vhdl代码 使用quartus编译 cpu中 alu的设计 可作为课程设计的参考 此为16的运算器

library IEEE;
library UNISIM;
use UNISIM.VComponents.all;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ALU is
 port(
 	T2: in std_logic;
	CLK: in std_logic;
	RST: in std_logic;
	Rupdate: in std_logic;
	Radd: in std_logic_vector(2 downto 0);
	Rdata: in std_logic_vector(7 downto 0);
	IRout: in std_logic_vector(15 downto 0);
	MRD_C: out std_logic;
	MWR_C: out std_logic;
	Addr: out std_logic_vector(15 downto 0);
	ALUout: out std_logic_vector(7 downto 0));
end ALU;

architecture Behavioral of alu is
	type register_array is array(0 to 7) of std_logic_vector(7 downto 0);
	signal temp1, temp2: std_logic_vector(7 downto 0);
begin
	process(T2, Rupdate, CLK, IRout, RST, Rdata)
		variable registers: register_array;
	begin
	    	temp1 <= registers(conv_integer(IRout(10 downto 8)));
	    	temp2 <= registers(conv_integer(IRout(2 downto 0)));
      	Addr(15 downto 8) <= registers(7);
      	Addr(7 downto 0) <= IRout(7 downto 0);
		if(RST = '1') then
			for i in 0 to 7 loop
				registers(i) := (others => '0');
			end loop;
	    	elsif(Rupdate = '1')then
	    		registers(conv_integer(Radd)) := Rdata;
	    	end if;
	end process;

	process(T2, clk)
	begin
		if(CLK'event and CLK = '1')then
	    		if(T2 = '1')then
	    			case IRout(15 downto 11) is
	    				when "00000" => ALUout <= temp1 + temp2; --ADD
					when "00010" => ALUout <= temp1 - temp2; --SUB
					when "00100" => ALUout <= temp1 and temp2; --AND 
					when "00110" => ALUout <= temp1 or temp2; --OR
					when "01000" => ALUout <= temp2; --MOV
					when "01010" => ALUout <= IRout(7 downto 0); --MVI
					when "01100" => ALUout <= temp1; --STA
					when "01110" => NULL; --LDA
					when others =>
						if(temp1 = "00000000") then
							ALUout <= (others => '0');
						end if;
	    		   	end case;
	    	   	end if;
		end if;
	end process;
	MWR_C <= '1' when IRout(15 downto 12) = "0110" else '0';
	MRD_C <= '1' when IRout(15 downto 12) = "0111" else '0';
end Behavioral;