xmit.vhdl

xilinx环境下开发vhdl语言串行接口设计

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity xmit is
    Port ( clrn : in std_logic;
	        tdata : in std_logic_vector(7 downto 0);
           clktr : in std_logic;
           txd : out std_logic;
           xmitting : out std_logic;
           done_xmitting : out std_logic;
           enclk : out std_logic);
end xmit;

architecture main of xmit is
	 signal count : std_logic_vector(3 downto 0);
begin
	  process(clrn)
	  begin
		if clrn='0' then
		 	 enclk<='0';
      else  
		    enclk<='1';
      end if;
     end process;

	  process(clrn,clktr)
	  begin		 
	    if  clrn='0'  then 
		     count<="0000";
       elsif clktr='1' and clktr'event  then 
		    count<=count+1;
		    if count="1100"  then 
			   count<="0000";
			 end if;
       end if;
     end process;

	  process(count,clrn)
	  begin
	   if  clrn='0'  then
		    xmitting<='0';
			 done_xmitting<='0';
			 txd <= '1';
      else
        case count is
		    when  "0000" =>  NULL;
		    when  "0001" =>  txd<='0';   xmitting<='1';   done_xmitting<='0';
			 when  "0010" =>  txd<=tdata(0);
			 when  "0011" =>  txd<=tdata(1);
			 when  "0100" =>  txd<=tdata(2);
			 when  "0101" =>  txd<=tdata(3);
			 when  "0110" =>  txd<=tdata(4);
			 when  "0111" =>  txd<=tdata(5);
			 when  "1000" =>  txd<=tdata(6);
			 when  "1001" =>  txd<=tdata(7);
			 when  "1010" =>  txd<='1';   xmitting<='0'; 
			 when  others =>   done_xmitting<='1';
       end case;
		end if;
     end process;

end main;