bps.vhdl

xilinx环境下开发vhdl语言串行接口设计

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity bps is
    Port ( clk : in std_logic;
           enclk : in std_logic;
           clktr : out std_logic);
end bps;

architecture main of bps is
	 signal  count : std_logic_vector(7 downto 0);
	 signal   temp : std_logic	 :='0';
begin
     process(enclk,clk)
	  begin
	  if  enclk='0'  then
	    count<="00000000";
		 temp<='0';
		 clktr<=not temp;
	  elsif  clk='1' and clk'event  then
	        
		     if  count="00000001"  then 
		     	   temp<= not temp;
					clktr<=temp;
               count<="00000000";
           else   
			      count<=count+1; 
		     end if;

	   end if;
	 end process;
end main;