ctrl.vhdl

xilinx环境下开发vhdl语言串行接口设计

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ctrl is
    Port ( rst : in std_logic;
           npreq : in std_logic;
           nprd : in std_logic;
           npwr : in std_logic;
           ioab : in std_logic_vector(1 downto 0);
           iodb : inout  std_logic_vector(7 downto 0);
           tdata : out std_logic_vector(7 downto 0);
           rdata : in std_logic_vector(7 downto 0);
           rcving : in std_logic;
           done_rcving : in std_logic;
           xmitting : in std_logic;
           done_xmitting : in std_logic;
			  sclrn : out std_logic);
end ctrl;

architecture main of ctrl is
	  signal  rcv,xmitt,drcv,dxmitt : std_logic;
begin
	  process(rst,npreq,nprd,npwr,rdata,rcving,done_rcving,xmitting,done_xmitting)
	   begin
		rcv<=rcving;
		drcv<=done_rcving;
		xmitt<=xmitting;
		dxmitt<=done_xmitting;
		 if  rst='0'  then 
		  	  tdata<="00000000";
			  iodb<="ZZZZZZZZ";
			  rcv<='0';
			  xmitt<='0';
			  drcv<='0';
			  dxmitt<='0';
			  sclrn<='0';
		 else 	
		      if  npreq='1' then
		             iodb<="ZZZZZZZZ";
				elsif   nprd='0'   and ioab="00" and  drcv='1'  and rcv='0' then
		     		    iodb <= rdata;	  
						     drcv <= '0' ;
		      elsif   npwr='0' and ioab="00" and dxmitt='1' and  xmitt='0' then
		                 tdata <= iodb;	 sclrn<='1';
		      elsif  	npwr='0' and  ioab="11" and drcv='1'   then
					        tdata<="00000000";
			              iodb<="ZZZZZZZZ";
			              rcv<='0';
			              xmitt<='0';
			              drcv<='0';
			              dxmitt<='0';
            elsif  	nprd='0' and ioab="01"  then
					         iodb(0)<=drcv;
				          	iodb(1)<=dxmitt;
					         iodb(2)<=xmitt;
				         	iodb(3)<=rcv;
				         	iodb(4)<='0';
				         	iodb(5)<='0';
                     	iodb(6)<='0';
              	        iodb(7)<='0';
            end if;
        end if;
      end process;
end main;